High test coverage is critical to manufacturing a competitive integrated circuit. Design-for-test infrastructure, however, increases the power-performance-area of a chip. This research describes an approach to reduce scan test overhead based on circuit topology heuristics. The heuristics are applied on full-scan designs to convert a subset of the scan flip-flops to D flip-flops, and then evaluated on robust K longest path per gate (KLPG) test patterns. These patterns are modified with multicycle path extension, to minimize test coverage loss even with high scan cell conversion rates. The results are demonstrated using the ISCAS89 and ITC99 benchmark circuits.

The minimum voltage of operation (Vmin) for memory arrays often limits the lowest system operating voltage. This paper introduces a novel read assist topology for a domino-based evaluation architecture in a read only memory (ROM). The implementation incorporates an assist pull-down (PD) device, which activates during the evaluation phase in order to increase the effective pull-down strength of the bit cells. This implementation maintains Vmin without increasing the size of pull down devices inside the bit cells. The assist topology improves read delay by 11-30% and increases noise margin. Area overhead can be limited to 27% in a typical ROM.