The channel knowledge map (CKM) is regarded as a digital twin of the wireless channel and provides location-specific channel information for environment-aware wireless communications. The channel gain map (CGM) is a typical form of CKM that stores spatially indexed channel gains over a target area, enabling fast link scheduling, coverage planning, and beam selection. Existing CGM construction methods mainly rely on propagation modeling or data-driven spatial completion, which can be computationally expensive or may inadequately capture site-specific propagation characteristics, thereby limiting prediction accuracy. To address this issue, we propose a three-stage Transformer-based CGM construction framework for predicting channel gains at arbitrary locations. In the first stage, the city map is discretized into grids, and the channel gain values within each grid are normalized to facilitate continuous spatial prediction. In the second stage, a Transformer-based coarse CGM prediction method is proposed to extract environmental features from the city map and generate a coarse CGM. In the third stage, a lightweight refinement network is designed, which leverages a small number of sparse measurements to refine the coarse predictions. Simulation results demonstrate that the proposed method significantly outperforms the state-of-the-art approaches across all performance metrics. In particular, compared with the existing optimal scheme, the proposed method achieves 32.81% and 20.63% reductions in normalized mean square error (NMSE) and root mean square error (RMSE), respectively, while improving the structural similarity index (SSIM) and peak signal-to-noise ratio (PSNR) by 2.08% and 3.71%, respectively.

In this paper, a reconfigurable intelligent surface (RIS)-assisted millimeter-wave (mmWave) communication system with hybrid beamforming is considered, where the base station (BS) transmits signals to users via the RIS. Due to the difficulty in acquiring accurate channel state information (CSI) and the high complexity of hybrid beamforming design, a codebook-based method is employed to balance communication performance and computational cost. However, conventional codebook construction typically neglects the influence of surrounding communication environments, resulting in poor adaptability in complex mmWave scenarios. Therefore, we propose a three-stage environment-aware codebook design framework based on channel knowledge map (CKM) to enhance the adaptability of systems under different channel conditions. Specifically, in the first stage, a deep learning (DL)-based method is proposed to construct the CKM, which is a site-specific database that provides accurate CSI for given locations. In the second stage, the CSI of potential users is rapidly acquired based on the CKM, then a deep reinforcement learning (DRL) algorithm is employed to generate environment-aware codebooks by solving a sum achievable rate maximization problem. In the third stage, the end-to-end composite channel is first estimated. Then, the digital beamforming is computed by using the minimum mean square error (MMSE) criterion. Finally, the optimal analog beamforming and RIS phase shifts are selected through codebook scanning. Simulation results demonstrate that the proposed CKM-based environment-aware codebooks significantly outperform other codebook schemes in terms of sum achievable rate.

A novel design approach is presented to extend the bandwidth and output power back-off (OBO) range of symmetric Doherty power amplifier. The traditional single variable regulation techniques are effective for output power back-off range extension only at single frequency points. Firstly, one phase dispersion (PD factor) is introduced to characterize the OBO range versus frequency. Secondly, multi-parameters optimization of PD factor, complex combining load (CCL), and out-phased current combining (OCC) is used to alleviate the conflict of bandwidth and OBO range. Dynamically optimizing frequencydependent CCL and OCC parameters to counteract the dispersion effect of the matching network thus enable the wideband OBO extension and expanding design flexibility of symmetric DPA. For demonstration, a symmetric DPA with 9dB OBO range is proposed with a fractional operation bandwidth of 36% within 1.8-2.6 GHz. Under the continuous-wave excitation, the fabricated DPA features a 9-dB output back-off (OBO) efficiency of 37.9%– 55% and a saturated efficiency of 55.7%–66.9%, respectively. When driven by a 20-MHz long-term evolution (LTE) modulated signal with 9-dB peak-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than -50.1 dBc after digital predistortion.

This paper proposes a millimeter-wave (mmW) oscillator with “$2+1$” cores and triple operation modes to realize an octave-tuning range. An auxiliary core, comprising a switch and a negative transconductance cell, is introduced to the regular dual-core oscillator to generate a third mode with enhanced effective Q. This auxiliary core not only broadens the tuning range without compromising phase noise or chip area but also avoids the risk of introducing mismatch into two regular cores like triple-core oscillators. The demand for low interconnect resistance is relieved because of the merits of less core mismatch and extra magnetic injection lock path. The behavior of the proposed oscillator in different modes is studied analytically. A quantitative analysis of phase noise and interconnect resistance in the dual-core oscillator is presented and verified against circuit simulations. Implemented in a 65-nm CMOS process, the oscillator achieves a 72.24% tuning range from 16.35 to 35.48 GHz and a peak figure-of-merit of tuning range and area (FoM$_{\mathrm {TA}}$) of -217.07 dBc/Hz at 20.27 GHz with 1 MHz frequency offset. The chip operates from a 1 V supply with a power consumption from 6.3 to 21.76 mW and a core area of 0.075 mm2.

This paper presents a 6-bit bidirectional variable-gain vector-summing active phase shifter (BVG-AVSPS) in TSMC 65nm CMOS technology. The proposed BVG-AVSPS consists of a novel bidirectional quadrature generator, four dual-function bidirectional amplifiers and two input/output matching networks. The proposed hybrid-based quadrature generator achieves low orthogonal amplitude and phase mismatches over a wideband with bidirectionality. Dual-function bidirectional amplifiers are employed to achieve either vector modulation or gain control functions in different operational directions. To improve the phase shifting accuracy during gain tuning, compensation transistors are employed in the dual-function bidirectional amplifiers to minimize additional phase variation. The proposed input/output networks based on L-type coupled inductors ensure proper impedance matching for both input and output in TX and RX modes. For both TX and RX modes over 24 GHz~32 GHz, the measured RMS phase and gain errors are 1.25∘~2.4∘and 0.42 dB~0.56 dB throughout 12.3 dB gain tuning range, respectively. With the help of the compensation transistors, measured phase variation is less than ±2.1∘during output gain tuning. The core area of proposed BVG-AVSPS is 625 µm×355 µm.

This paper presents a compact PIN-diode-based single-pole double-throw (SPDT) switch for wideband RF systems. The series-shunt topology is adopted for the proposed switch. Compensating inductors are introduced to parallelly resonate with the off-capacitance of series diodes, creating an isolation peak. A two-pole highpass matching network is realized by introducing an additional inductor and reusing existing DC components, which ensures compact size and wideband capability. Moreover, the matching network enables independent control of ON-state operating band over the OFF-state, allowing optimized insertion loss and isolation at the desired center frequency. To assist analytical design, closed-form equations of the highpass matching network are derived through equivalent circuit analysis. For demonstration, one SPDT switch utilizing commercial PIN diodes and lumped RLC components is designed, fabricated, and measured. The measured results exhibit superior return loss of better than 20dB across 1.02-3.36 GHz attributed to the two-pole response. The insertion loss remains below 0.81 dB, reaching 0.457 dB at 2.6 GHz, while isolation is better than 27 dB, with a maximum of 71.8 dB at 2.25 GHz. Importantly, the proposed design can be scaled to mm-wave bands with better performances than their widely developed lowpass counterpart.

In this paper, a reconfigurable intelligent surface (RIS) is utilized to assist wireless-powered communication network (WPCN) for achieving integrated sensing and communication (ISAC). In this system, the ISAC base station (BS) first performs radar sensing for multiple targets and wireless power transfer (WPT) for multiple energy-constrained devices with assistance of RIS during the downlink (DL), then all devices transmit their data to the ISAC BS in the uplink (UL) by employing non-orthogonal multiple access (NOMA) with the use of harvested energy. To maximize the sum achievable throughput subject to the quality of service (QoS) constraints of communication devices and sensing quality constraint of targets, we jointly optimize the energy beamforming matrix, radar beamforming matrix, phase shift matrix of RIS, and transmission timeslot allocation in the DL and UL durations. To tackle this non-convexity problem, a two-stage solution is proposed. In the first stage, the energy and radar beamforming matrices, and phase shift matrix of RIS in the DL can be derived according to the penalty-based successive convex approximation (SCA) algorithm and Riemannian conjugate gradient (RCG) algorithm, respectively. In the second stage, the transmission timeslot allocation and phase shift matrix of RIS in the UL are obtained via the polar point method and penalty-based RCG algorithm, respectively. The final optimal results of each stage are yielded based on alternating optimization (AO) algorithm. Numerical results verify the significant improvement of deploying RIS for WPT and data transmission, and the superiority of the proposed optimization solution in improving the sensing performance and achievable throughput compared to other schemes.

While single reconfigurable intelligent surface (RIS)- aided systems have demonstrated potential in improving transmission performance, their ability to serve multi-user scenarios is inherently limited. In this paper, we investigate the deployment of multiple RISs to assist downlink (DL) millimeter-wave (mmWave) non-orthogonal multiple access (NOMA) communications between a base station (BS) and multiple users. For maximizing the system achievable throughput, we propose a two-stage resource allocation scheme. In the first stage, a two-step RIS-user pairing scheme is proposed by combining the Gale-Shapley (GS) algorithm and the worst connection swapping (WCS) algorithm. In the second stage, based on the pairing results from the first stage, an alternating optimization (AO) algorithm is utilized to iteratively optimize RIS phase shifts, digital precoder, and power allocation. During each iteration, with fixed digital precoder and arbitrary feasible power allocation, the optimal RIS phase shifts can be obtained by the difference of convex (D. C.) programming and semidefinite relaxation (SDR) techniques. Then, the minimum mean-squared error (MMSE)-based digital precoder is adopted. Based on the derived RIS phase shifts and digital precoder, the optimized power allocation can be derived by reusing the D. C. programming subject to the constraint of decoding rate for successive interference cancellation (SIC). Simulation results show that the proposed pairing scheme can achieve near-optimal system achievable throughput, while significantly reducing the computational complexity. In addition, the proposed two-stage resource allocation scheme also demonstrates advantages in improving the overall achievable throughput of the system.

In this paper, a reconfigurable intelligent surface(RIS)-assisted millimeter-wave (mmWave) non-orthogonal multiple access (NOMA) communication system is considered, where the RIS is virtually partitioned into several sub-RISs to serve different user clusters. We aim to maximize the sum achievable rate of the considered system by jointly optimizing user clustering, RIS partitioning, active beamforming, passive beamforming, and power allocation, subject to the quality-of-service (QoS) requirements of each user and the maximum transmit power constraint of the base station (BS). To tackle the formulated non-convex joint optimization problem, a three-stage algorithm based on machine learning (ML) is proposed. In the first stage, user clustering is performed by combining the K-means algorithm and the Gaussian mixture model (GMM). In the second stage, a deep learning (DL)-based RIS partitioning method is proposed, which utilizes double cascaded deep neural networks (DNNs) to partition the RIS into multiple sub-RISs virtually, each of which serves a user cluster. In the third stage, a deep reinforcement learning (DRL) algorithm based on deep deterministic policy gradient (DDPG) is invoked to obtain the active beamforming, passive beamforming, and power allocation. Simulation results demonstrate that the proposed RIS partitioning method can effectively improve the utilization of RIS and thereby increase the total throughput of the system. Moreover, the sum achievable rate obtained by the proposed ML-based three-stage algorithm is higher than that of the conventional alternating optimization (AO) algorithm.

In this paper, a reconfigurable intelligent surface (RIS)-assisted millimeter-wave (mmWave) multi-hop communication system is considered, where the base station (BS) transmits signals to remote users via multi-hop paths formed by multiple RISs. We aim to maximize the sum achievable rate by jointly optimizing multi-hop path scheduling, active beamforming, and passive beamforming, while satisfying the maximum transmit power of the BS. To tackle the formulated non-convex joint optimization problem, a machine learning (ML)-based two-stage algorithm is proposed. In the first stage, a multi-hop path scheduling algorithm based on graph neural networks (GNN) is investigated. Specifically, the considered system is first modeled as a graph topology, where the BS, RIS, and users are all served as nodes. Then, the weights between adjacent nodes associated with the path gain and the number of RIS reflection units are defined based on the expressions of RIS-assisted equivalent channels. Finally, a GNN-based multi-hop path scheduling algorithm is proposed. In the second stage, according to the obtained optimal multi-hop path, the deep deterministic policy gradient (DDPG) strategy is adopted to optimize the active beamforming of the BS and the passive beamforming of the selected RISs. Simulation results demonstrate that the proposed GNN-based multi-hop path scheduling algorithm maintains an error within 3% compared to the global optimal solution and outperforms the graph-based methods. Additionally, the proposed two-stage algorithm improves the sum achievable rate by approximately 27.6% compared to the alternating optimization (AO) algorithm.

Charging scheduling plays a crucial role in ensuring durable operation for wireless rechargeable sensor networks. However, previous methods cannot meet the strict requirements of a high node survival rate and high energy usage effectiveness. In this article, we propose a multi-type charging scheduling strategy to meet such demands. In this strategy, the network is divided into an inner ring and an outer ring to satisfy different demands in different areas. The inner ring forms a flat topology, and adopts a periodic and single-node charging pattern mainly for a high node survival rate. A space priority and a time priority are designed to determine the charging sequence of the nodes. The optimal charging cycle and the optimal charging time are achieved by mathematical derivations. The outer ring forms a cluster topology, and adopts an on-demand and multi-node charging pattern mainly for high energy usage effectiveness. A space balancing principle and a time balancing principle are designed to determine the charging positions of the clusters. A gravitational search algorithm is designed to determine the charging sequence of the clusters. Several simulations verify the advantages of the proposed solution in terms of energy usage effectiveness, charging failure rate, and average task delay.

A design strategy to enhance the efficiency of the dual-mode Doherty power amplifier (DPA) is proposed. The continuous multiple harmonic regulation approach is adopted to realize high efficiency of dual-mode DPA in a wide operating frequency band. Multi-harmonic control and dual-mode impedance matching are performed by a single load modulation network. The DPA’s operating frequency band and harmonic control type can be simultaneously switched through reciprocal gate bias. A DPA using GaN devices with continuousClass$F$for Mode I (1.5–2.4 GHz) andClass$J$/continuous inverseClass$F$for Mode II (1.3–1.4 GHz/2.5–2.7 GHz) is designed and implemented. The fabricated DPA achieves a measured 10.5–14.3-dB gain and 39.2–41.8-dBm saturated power. Due to the proposed strategies, 39.1%–58.2% and 55.6%-71.9% drain efficiencies are obtained respectively at 6-dB output power back-off and saturation output power for the designed DPA. For the down-link long-term evolution (LTE) signal with a channel bandwidth of 20 MHz and a peak-to-average power ratio (PAPR) of 7.5 dB, the average adjacent channel power ratio of the fabricated DPA is better than 40 dBc after digital predistortion at 1.3, 2.0 and 2.6 GHz with average output power back-off (OBO) efficiency of 37.8%, 39.3% and 43.3%.

This paper presents a high-flexibility and low-cost transceiver (TRX) in 65-nm CMOS process for fifth-generation (5G) communications. The TRX is based on local-oscillator (LO) phase-shifting architecture with 5 bits of gain control and 6 bits of phase control. To enhance the transceiver gain, bandwidth, efficiency, noise performance, and achieve ultra-low amplitude and phase errors without any calibration, a variety of innovative techniques are introduced in this work. The TX path demonstrates a measured peak conversion gain (CG) of 43.1 dB with the IF fractional bandwidth of 79% from 3.5 to 8.1 GHz and the RF of20% from 23.4 to 28.5 GHz. The measured TX OP1dB is up to 13.3 dBm at26 GHz. In the RX mode, the measured peak CG is 29.6 dB with 134% fractional bandwidth of the IF (2.1 to 10.6 GHz), 19% of the RF (23.7 to 28.6 GHz) and the minimum noise Figure is 5.5 dB (including T/R switch). Moreover, the TRX with 6-bit phase resolution realizes a measured RMS amplitude and phase errors of less than 0.63 dB and 2. 4°, respectively. The proposed wideband transceiver simultaneously implements broadband RF/LO/IF while maintaining ultra-low gain and phase errors without any calibration. Such a system with only one chip can meet the requirements of IF, LO and RE frequency combinations of different scenarios, which is suitable for high data-rate and low cost 5G applications.

In this paper, two types of balanced-to-unbalanced quadrature couplers with six hybrid ports and arbitrary power division ratio are proposed. For Type 1, the quadrature coupler can realize two power division functions, including balanced/unbalanced to balanced-unbalanced-hybrid, and for Type 2, the quadrature coupler contains balanced -to-unbalanced and unbalanced-to-balanced power division functions. To reduce the circuit size, double-sided parallel-strip line (DSPSL) swap structure is used to replace the half-wavelength transmission line, and compact circuit size can be easily achieved. To validate the performance of the quadrature couplers, two types of the balanced-to-unbalanced quadrature couplers centered at 1 GHz with power division ratios 1:1 and 3:1 are fabricated and measured, respectively. The common mode suppression higher than 10 dB (bandwidths over than 176%) can be realized, the isolation and in-band matching level can be also improved.

An odd-element half-wave-rectification superposition (OHS) technique is presented and verified for designing the high-multiplication factor frequency multipliers. The proposed OHS technique superposes N odd-element phase-shifted half-wave-rectification (HWR) fundamental signals ($f_{0}$) to extract the 2N-order harmonic (2N$f_{0}$) while canceling the fundamental ($f_{0}$) and the 2ndto (2N-1)th harmonics without extra filtering. Compared with the reported even-element half-wave-rectification superposition technique (EHS) technique, the proposed OHS technique can realize the same multiplication factor but requires only a half number of the input HWR signals. Thus, the proposed OHS technique can be applied to design the high-multiplication factor frequency multiplier that is difficult to be implemented using the reported EHS technique. To verify the validity of the proposed OHS technique, a differential$\times 6$frequency multiplier with the input frequency range of 5-7GHz and output frequency range of 30–42 GHz was implemented in 65 nm CMOS process. The experimental results indicate that the implemented$\times 6$frequency multiplier exhibits more than 23 dBc rejection to the fundamental and 2ndto 5thharmonics without the extra filter. The DC power consumption is 4.6 mW for the core circuit.

An simplified vector-sum phase shifter (VSPS) topology is proposed in this article. The proposed VSPS topology employs only one 90° coupler to perform as both an I/Q generator and a vector summer. Compared with the literaturally reported VSPS, the proposed VSPS features a simpler topology and improved noise figure (NF) performance. Moreover, active baluns based on the self-calibration technique are employed to provide antiphase signals and improve the gain performance of the VSPS. For demonstration, a 24–30-GHz VSPS based on the proposed topology is implemented in the 65-nm CMOS process, exhibiting 3.5° rms phase error and 0.9-dB rms gain error. The average gain of the implemented VSPS is as high as 9 dB at the central frequency of 27 GHz. The NF ranges from 4.8 to 9 dB from 24 to 30 GHz, and the core chip size is$0.36\times0.59$mm2.

A 9.8–30.1 GHz CMOS low-noise amplifier (LNA) with a 3.2-dB minimum noise figure (NF) is presented. At the architecture level, a topology based on common-gate (CG) cascading with a common-source (CS) amplifier is proposed for simultaneous wideband input matching and relatively high gain. At the circuit level, multiple techniques are proposed to improve LNA performance. First, in the CG stage, loading effect is properly used instead of the conventional feedback technique, to enable simultaneous impedance and noise matching. Second, based on in-depth theoretical analysis, the inductor- and transformer-based g m -boosting techniques are employed for the CG and CS stages, respectively, to enhance the gain and reduce power consumption. Third, the floating-body method, which was originally proposed to lower NF in CS amplifiers, is adopted in the CG stage to further reduce NF. Fabricated in a 65-nm CMOS technology, the LNA chip occupies an area of only 0.2 mm 2 and measures a maximum power gain of 10.9 dB with −3 dB bandwidth from 9.8 to 30.1 GHz. The NF exhibits a minimum value of 3.2 dB at 15 GHz and is below 5.7 dB across the entire bandwidth. The LNA consumes 15.6 mW from a 1.2-V supply.