High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module from scratch in SystemC and SystemVerilog based on a desired architecture. Additionally, we develop micro-benchmarks to demonstrate best-practices in C coding styles that produce high-quality hardware with minimal development effort. Finally, we suggest language, tool, and methodology improvements to improve upon the current state-of-the-art in HLS.

This paper presents the first SPICE model of the transition metal dichalcogenide (TMD) field-effect transistor (FET), which is a promising candidate for flexible electronics. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials (MoS2, WSe2, etc.), as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. We performed SPICE simulations on digital logic gates to explore the design space of both MoS2- and WSe2-based transistors, and to evaluate the projected performance of these circuits under applied strain. Our simulations show that WSe2 circuits outperform MoS2 and Si-based CMOS in terms of energy-delay product (EDP) by 1 order of magnitude or more, depending on applications. Finally, we investigate TMDFET's behavior under process variation.