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Tingzhe Zhou

dblp:163/7054 · DBLP profile ↗
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11ranked-venue papers
6as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 9 · 5 first-authorSecurity and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Web and mobile security · 67% Systems and software security · 33%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 77% Compilers and program optimization · 23%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming
transactional memory
0.412019
Simplifying Transactional Memory Support in C++ · ACM Trans. Archit. Code Optim. 2019
Web and mobile security › browser security
content security policy
0.212016
CSPAutoGen: Black-box Enforcement of Content Security Policy upon Real-world Websites · CCS 2016
Systems and software security › exploitation › injection attacks › code injection attack
cross-site scripting prevention
0.212016
CSPAutoGen: Black-box Enforcement of Content Security Policy upon Real-world Websites · CCS 2016
Web and mobile security
web application security
0.212016
CSPAutoGen: Black-box Enforcement of Content Security Policy upon Real-world Websites · CCS 2016
Compilers and program optimization › compiler construction
compiler support for transactional memory
0.112019
Simplifying Transactional Memory Support in C++ · ACM Trans. Archit. Code Optim. 2019

Methods — techniques the papers use, named apart from their topics

hardware transactional memory · 0.4executor-based transaction execution · 0.4template learning · 0.2dynamic rewriting · 0.2
YearPublicationVenuePosition
2019 Optimizing Persistent Memory Transactions
abstract
Byte-addressable, non-volatile, random access memory (NVM) has the potential to dramatically accelerate the performance of storage-intensive workloads. For applications with irregular data access patterns, and applications that rely on ad-hoc data structures, the most promising model for interacting with NVM is a transactional model. However, the specifics of the model matter significantly. We introduce two models for programming persistent transactions. We show how to build concurrent persistent transactional memory from traditional software transactional memories. We then introduce general and model-specific optimizations that can substantially improve the performance of persistent transactions. Our evaluation shows a substantial improvement in the both the latency and scalability of persistent transactions.
Pantea Zardoshti, Tingzhe Zhou, Yujie Liu 0003, Michael F. Spear
PACT2
2019 A Practical, Scalable, Relaxed Priority Queue
abstract
Priority queues are a fundamental data structure, and in highly concurrent software, scalable priority queues are an important building block. However, they have a fundamental bottleneck when extracting elements, because of the strict requirement that each extract() returns the highest priority element. In many workloads, this requirement can be relaxed, improving scalability.
Tingzhe Zhou, Maged M. Michael, Michael F. Spear
ICPP1
2019 Optimizing Persistent Transactions (Brief Announcement)
abstract
There is a mechanical transformation by which algorithms for software transactional memory can be transformed to work with persistent memory. While correct, this transformation does not take into account differences between the persistent and volatile programming models. We show that fundamental properties of the data regions accessed by a persistent software transaction allow for a variety of optimizations not available in the volatile setting, and these lead to significant performance gains.
Tingzhe Zhou, Pantea Zardoshti, Michael F. Spear
SPAA1
2019 Simplifying Transactional Memory Support in C++
abstract
C++ has supported a provisional version of Transactional Memory (TM) since 2015, via a technical specification. However, TM has not seen widespread adoption, and compiler vendors have been slow to implement the technical specification. We conjecture that the proposed TM support is too difficult for programmers to use, too complex for compiler designers to implement and verify, and not industry-proven enough to justify final standardization in its current form. To address these problems, we present a different design for supporting TM in C++. By forbidding explicit self-abort, and by introducing an executor-based mechanism for running transactions, our approach makes it easier for developers to get code up and running with TM. Our proposal should also be appealing to compiler developers, as it allows a spectrum of levels of support for TM, with varying performance, and varying reliance on hardware TM support in order to provide scalability. <?tight?>While our design does not enable some of the optimizations admitted by the current technical specification, we show that it enables the implementation of robust support for TM in a small, orthogonal compiler extension. Our implementation is able to handle a wide range of transactional programs, delivering low instrumentation overhead and scalability and performance on par with the current state of the art. Based on this experience, we believe our approach to be a viable means of reinvigorating the standardization of TM in C++.
Pantea Zardoshti, Tingzhe Zhou, Pavithra Balaji, Michael L. Scott, Michael F. Spear
ACM Trans. Archit. Code Optim.2
2017 Redesigning Go's Built-In Map to Support Concurrent Operations
abstract
The Go language lacks built-in data structures that allow fine-grained concurrent access. In particular, its map data type, one of only two generic collections in Go, limits concurrency to the case where all operations are read-only; any mutation (insert, update, or remove) requires exclusive access to the entire map. The tight integration of this map into the Go language and runtime precludes its replacement with known scalable map implementations.This paper introduces the Interlocked Hash Table (IHT). The IHT is the result of language-driven data structure design: it requires minimal changes to the Go map API, supports the full range of operations available on the sequential Go map, and provides a path for the language to evolve to become more amenable to scalable computation over shared data structures. The IHT employs a novel optimistic locking protocol to avoid the risk of deadlock, and allows large critical sections that access a single IHT element, and can easily support multikey atomic operations. These features come at the cost of relaxed, though still straightforward, iteration semantics. In experimentation in both Java and Go, the IHT performs well, reaching up to 7× the performance of the state of the art in Go at 24 threads. In Java, the IHT performs on par with the best Java maps in the research literature, while providing iteration and other features absent from other maps.
Louis Jenkins, Tingzhe Zhou, Michael F. Spear
PACT2
2017 Practical Experience with Transactional Lock Elision
abstract
Transactional Memory (TM) promises both to provide a scalable mechanism for synchronization in concurrent programs, and to offer ease-of-use benefits to programmers. The most straightforward use of TM in real-world programs is in the form of Transactional Lock Elision (TLE). In TLE, critical sections are attempted as transactions, with a fall-back to a lock if conflicts manifest. Thus TLE expects to improve scalability, but not ease of programming. Still, until TLE can deliver performance improvements, transactional styles of programming are unlikely to gain popularity.In this paper, we describe our experiences employing TLE in two real-world programs: the PBZip2 file compression tool, and the x265 video encoder/decoder. We discuss the obstacles we encountered, propose solutions to those obstacles, and introduce open challenges. In experiments using the GCC compiler's hardware and software support for TM, we observe that both are able to outperform the original lock-based code, potentially heralding the readiness of TM to be used more broadly for TLE, if not for truly transactional styles of programming.
Tingzhe Zhou, Pantea Zardoshti, Michael F. Spear
ICPP1
2017 Extending Transactional Memory with Atomic Deferral
abstract
This paper introduces atomic deferral, an extension to TM that allows programmers to move long-running or irrevocable operations out of a transaction while maintaining serializability: the transaction and its de- ferred operation appear to execute atomically from the perspective of other transactions. Thus, program- mers can adapt lock-based programs to exploit TM with relatively little effort and without sacrificing scalability by atomically deferring the problematic operations. We demonstrate this with several use cases for atomic deferral, as well as an in-depth analysis of its use on the PARSEC dedup benchmark, where we show that atomic deferral enables TM to be competitive with well-designed lock-based code.
Tingzhe Zhou, Victor Luchangco, Michael F. Spear
OPODIS1
2017 Hand-Over-Hand Transactions with Precise Memory Reclamation
abstract
In this paper, we introduce revocable reservations, a transactional memory mechanism to reserve locations in one transaction and check whether they are unchanged in a subsequent transaction without preventing reserved locations from being reclaimed in the interim. We describe several implementations of revocable reservations, and show how to use revocable reservations to implement lists and trees with a transactional analog to hand-over-hand locking. Our evaluation of these data structures shows that revocable reservations allow precise and immediate reclamation within transactional data structures, without sacrificing scalability or introducing excessive latency.
Tingzhe Zhou, Victor Luchangco, Michael F. Spear
SPAA1
2017 Brief Announcement: Extending Transactional Memory with Atomic Deferral
abstract
Atomic deferral is a language-level mechanism for transactional memory (TM) that enables programmers to move output and long-running operations out of a transaction's body without sacrificing serializability: the deferred operation appears to execute as part of its parent transaction, even though it does not make use of TM.
Tingzhe Zhou, Victor Luchangco, Michael F. Spear
SPAA1
2016 CSPAutoGen: Black-box Enforcement of Content Security Policy upon Real-world Websites
abstract
Content security policy (CSP) which has been standardized by W3C and adopted by all major commercial browsers-is one of the most promising approaches for defending against cross-site scripting (XSS) attacks. Although client-side adoption of CSP is successful, server-side adoption is far behind the client side: according to a large-scale survey, less than 0.002% of Alexa Top 1M websites enabled CSP. To facilitate the adoption of CSP, we propose CSPAutoGen to enable CSP in real-time, without server modifications, and being compatible with real-world websites. Specifically, CSPAutoGen trains so-called templates for each domain, generates CSPs based on the templates, rewrites incoming webpages on the fly to apply those generated CSPs, and then serves those rewritten webpages to client browsers. CSPAutoGen is designed to automatically enforce the most secure and strict version of CSP without enabling "unsafe-inline" and "unsafe-eval", i.e., CSPAutoGen can handle all the inline and dynamic scripts.
Yinzhi Cao, Shuangping Liu, Yan Chen 0004, Tingzhe Zhou
CCS6
2015 Transactional Acceleration of Concurrent Data Structures
abstract
Concurrent data structures are a fundamental building block for scalable multi-threaded programs. While Transactional Memory (TM) was originally conceived as a mechanism for simplifying the creation of concurrent data structures, modern hardware TM systems lack the progress properties needed to completely obviate traditional techniques for designing concurrent data structures, especially those requiring nonblocking progress guarantees. In this paper, we introduce the Prefix Transaction Optimization (PTO) technique for employing hardware TM to accelerate existing concurrent data structures. Our technique consists of three stages: the creation of a prefix transaction, the mechanical optimization of the prefix transaction, and then algorithm-specific optimizations to further improve performance. We apply PTO to five nonblocking data structures, and observe speedups of up to 2x at one thread, and up to 3x at 8 threads.
Yujie Liu 0003, Tingzhe Zhou, Michael F. Spear
SPAA2