Linearity testing, including differential nonlinearity (DNL) and integral nonlinearity (INL), is of great significance to evaluate the performance of an analog-to-digital converter (ADC). However, highly linear signal generator and large amount of samples are two challenges in conventional histogram testing method. This paper proposes a segmentation nonlinear model with partial polynomial fitting to reduce the required samples, while the source nonlinearity removal scheme relaxes the precision requirement of signal generator. The influence of noise and source resolution are analyzed. Measurement results show that with a 12-bit digital-to-analog converter (DAC) and 393 216 samples, the 16-bit ADC INL and DNL can be measured with estimation errors less than 0.3 LSB.

This article presents a background calibration method for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). The proposed algorithm employs fast adaptive particle swarm optimization (FAPSO) to detect the timing skews in sub-channels and compensates them using second-order finite impulse response (FIR) differentiators. This approach enables simultaneous convergence of each channel and reduces the convergence time significantly. Hardware implementation of the proposed timing skew calibration is synthesized by field-programmable gate array (FPGA), and it consumes a total power of 7.3 mW. The effectiveness of the proposed FAPSO algorithm is verified through a commercial 12-bit 3.6-GS/s 4-channel TI-ADC. After applying FAPSO timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved by 16.5 and 29.6 dB, respectively.

A highly linear input buffer is crucial for high-speed and high-resolution analog-to-digital converters (ADCs) since it isolates the kickback noise and package inductance. Several important factors affecting the linearity of the input buffer are analyzed in this brief, and a wideband input buffer with high linearity based on cascade complementary source follower (CCSF) is proposed. This cascaded input buffer is composed of a pMOS source follower (PSF) and an nMOS source follower (NSF). Compensation capacitor, assisted operational amplifier (opamp), bootstrapped-capacitor level-shifting circuit, current amplifier, and optimization strategies are utilized to extend the bandwidth and reduce distortion. Designed in a 65-nm CMOS, the CCSF input buffer achieves the spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 76.6 and 58.1 dB with 1.9-GHz input frequency, respectively. It occupies 0.0155 mm$^2$and consumes 27 mW at 2.5 V.

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with$16\times $linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm2. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoMw) is 24.4 fJ/conversion-step.

This brief presents an 8-bit two-step successive approximation register analog-to-digital converter (SAR ADC), where the interstage gain is embedded in the second-stage comparison to eliminate the dedicated residue amplifier and its timing cost. Combined with the passive residue transfer technique, the prototype ADC realizes high speed while requiring small overhead. Fabricated in 28-nm CMOS, it operates at 1.5 GS/s and achieves an signal-to-noise-and-distortion-ratio (SNDR) of 43.3 dB at Nyquist rate while consuming 2.32 mW, resulting in a Walden figure-of-merit (FOM) of 12.9 fJ/conv-step.

This brief presents a single-channel 8-bit 1.5-GS/s voltage–time (V-T) hybrid two-step analog-to-digital converter (ADC). Benefiting from the fine quantification in the time domain, the power-to-noise requirement of a comparator and speed limitation in the voltage domain have been significantly relaxed. An efficient cross-coupled linearized technique (CCLT) is proposed in a dynamic voltage-to-time converter (VTC) design as a crucial part of this ADC. This technique helps improve the total harmonic distortion (THD) of VTC by 8 dB across most process–voltage–temperature (PVT) variations by avoiding using a power-harvest current-source (CS)-based VTC. Moreover, a dynamic conversion strategy is proposed in a time quantizer to build a more power-efficient design. Fabricated in a 28-nm CMOS process, the prototype ADC consumes 3.3 mW at 1-V supply with an active area of 0.0035 mm2. With a Nyquist input, it achieves a signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 45.4 and 60.3 dB, respectively, yielding a Walden figure of merit (FoMW) of 14.4 fJ/conversion-step.

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm2. Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step.

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.