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Milad Mohammadi

dblp:164/0815 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2020
0000-0001-5536-0247ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Energy-efficient computing · 53% Processor architecture and microarchitecture · 42% Cloud and datacenter computing · 4%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
branch prediction
0.412020
Energy Efficient On-Demand Dynamic Branch Prediction Models · IEEE Trans. Computers 2020
Energy-efficient computing › power management › device power management
processor power management
0.412020
Energy Efficient On-Demand Dynamic Branch Prediction Models · IEEE Trans. Computers 2020
Energy-efficient computing › low-power design
low-power processor design
0.312017
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance · ACM Trans. Archit. Code Optim. 2017
Processor architecture and microarchitecture
out-of-order execution
0.312017
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance · ACM Trans. Archit. Code Optim. 2017
Energy-efficient computing
power management
0.312017
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance · ACM Trans. Archit. Code Optim. 2017
Compilers and program optimization › compiler optimization
static branch prediction
0.112020
Energy Efficient On-Demand Dynamic Branch Prediction Models · IEEE Trans. Computers 2020
Cloud and datacenter computing › datacenter storage
block-level scheduling
0.112017
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance · ACM Trans. Archit. Code Optim. 2017
Processor architecture and microarchitecture
instruction scheduling
0.112017
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance · ACM Trans. Archit. Code Optim. 2017

Methods — techniques the papers use, named apart from their topics

simulation · 0.9SPEC Int 2006 benchmarks · 0.9compiler-level code optimization · 0.3
YearPublicationVenuePosition
2020 Energy Efficient On-Demand Dynamic Branch Prediction Models
abstract
The branch predictor unit (BPU) is among the main energy consuming components in out-of-order (OoO) processors. For integer applications, we find 16 percent of the processor energy is consumed by the BPU. BPU is accessed in parallel with the instruction cache before it is known if a fetch group contains control instructions. We find 85 percent of BPU lookups are done for non-branch operations, and of the remaining lookups, 42 percent are done for highly biased branches that can be predicted statically with high accuracy. We evaluate two variants of a branch prediction model that combines dynamic and static branch prediction to achieve energy improvements for power-constrained applications. These models, named on-demand branch prediction (ODBP) and path-based on-demand branch prediction (ODBP-PATH), are two novel prediction techniques that eliminate unnecessary BPU lookups using compiler generated hints to identify instructions that can be more accurately predicted statically. ODBP-PATH is an implementation of ODBP that combines static and dynamic branch prediction based on the program path of execution. For a 4-wide OoO processor, ODBP-PATH delivers 11 percent average energy-delay (ED) product improvement, and 9 percent core average energy saving on the SPEC Int 2006 benchmarks.
Milad Mohammadi, Song Han 0003, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally
IEEE Trans. Computers1
2017 CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance
abstract
We introduce the Coarse-Grain Out-of-Order (CG-OoO) general-purpose processor designed to achieve close to In-Order (InO) processor energy while maintaining Out-of-Order (OoO) performance. CG-OoO is an energy-performance-proportional architecture. Block-level code processing is at the heart of this architecture; CG-OoO speculates, fetches, schedules, and commits code at block-level granularity. It eliminates unnecessary accesses to energy-consuming tables and turns large tables into smaller, distributed tables that are cheaper to access. CG-OoO leverages compiler-level code optimizations to deliver efficient static code and exploits dynamic block-level and instruction-level parallelism. CG-OoO introduces Skipahead, a complexity effective, limited out-of-order instruction scheduling model. Through the energy efficiency techniques applied to the compiler and processor pipeline stages, CG-OoO closes 62% of the average energy gap between the InO and OoO baseline processors at the same area and nearly the same performance as the OoO. This makes CG-OoO 1.8× more efficient than the OoO on the energy-delay product inverse metric. CG-OoO meets the OoO nominal performance while trading off the peak scheduling performance for superior energy efficiency.
Milad Mohammadi, Tor M. Aamodt, William J. Dally
ACM Trans. Archit. Code Optim.1