Accurate respiratory monitoring is essential in critical care settings where abnormal breathing can indicate rapid deterioration and require immediate intervention. Existing non-invasive approaches face trade-offs in comfort, reliability, and portability, limiting their clinical applicability. Single Antenna Bio-Sensing (SABioS) offers an alternative by capturing local dielectric variations with a single wearable antenna, enabling comfortable, non-invasive monitoring of respiratory and cardiac activity. This work presents an implementation of SABioS on a compact custom PCB operating at 915 MHz in combination with a flexible sinusoidal dipole antenna sensor and a dedicated acquisition software, demonstrating the feasibility of portable, low-power, continuous monitoring. The system was evaluated against synchronized medical-grade reference devices, providing the first validation of SABioS for accurate cardiac activity detection in addition to respiration, with respiratory rate agreement of MoD ± LoA =$0.005~\pm ~0.217$bpm and heart rate agreement of MoD ± LoA =$0.0096~\pm ~0.322$bpm. Additional experiments confirmed stable operation of the system in long-term monitoring and robust performance across wearing configurations and body positions, including recumbent scenarios for sleep monitoring with up to 13.7 dB SNR improvement. Compared to the earlier proof-of-concept setups of SABioS, the integrated system achieves considerably higher signal-to-noise ratio and measurement accuracy, with up to +24.2 dB SNR improvement, underscoring its potential for continuous vital signs monitoring in practical healthcare applications.

System-on-chip (SoC) field programmable gate array (FPGA) devices are becoming increasingly prominent in a vast range of applications. The fusion of the FPGA’s unmatched parallel computing capacity and flexibility with a full-bore processing system makes these devices extremely powerful. With recent technological progress, SoC FPGA devices are implemented in increasingly complex systems where security and safety are often issues of concern. To cater to these concerns, these devices are commonly fit with encryption and authentication capabilities to ensure the confidentiality and authenticity of externally stored bitstreams, firmware, and bootloaders. However, while much effort is placed into securing these partitions when stored in external memory, little attention seems to be paid to the security of this data once it is decrypted for execution. This article investigates how vulnerable systems are to attacks that target decrypted data during execution. We demonstrate that data stored in external synchronous dynamic random access memory (SDRAM) can provide access to trusted and secured interfaces of SoC FPGA devices even with diligently applied security features.

Hardware-in-the-Loop (HIL) simulators play a critical role in the automotive industry by providing extensive testing and validation capabilities for electronic control units (ECUs). One of the main challenges faced by HIL simulators involves the task of constructing a virtual environment that accurately replicate the behavior of the actual system. Artificial intelligence (AI) algorithms can be useful in generating precise virtual environments for HIL simulations of complex systems. Moreover, minimal latency is essential for establishing a reliable virtual environment. FPGA (Field Programmable Gate Array) can effectively reduce latency in HIL simulations by providing high-performance computing resources. This paper aims to address these challenge by introducing a machine learning-driven HIL simulator implemented on FPGA. The proposed architecture employs FPGA technology to enhance the computational speed of a temporal convolutional neural network (TCN).

This article presents a critical literature review on the security aspects of field-programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. The article also pays special attention to emerging system-on-chip (SoC) FPGA devices that incorporate a hard processing system (HPS) on the same die as the FPGA logic. While this incorporation reduces the need for vulnerable external signals, the HPS in SoC FPGA devices adds a level of complexity that is not present for stand-alone FPGA devices. This added complexity necessarily hands over the task of securing the device to developers. Even with standard security features in place, the HPS might still have unhindered access to the FPGA logic. A single software flaw could open up a breach that might allow an attacker to extract the FPGA’s configuration data. A robust cybersecurity strategy is thus required for developers. As such, this work aims to provide the groundwork to build a solid threat-based cybersecurity design strategy that is specially adapted to SoC FPGA devices.

Proper acquisition of the photoplethysmography signals is essential in a pulse oximetry system and sensor placement plays an important role in this respect. Due to the complex structure of the finger tissue, inadequate sensor placement will have an adverse effect on the light path and high signal quality may become impossible to achieve [1]. In this paper, we present a ring shaped oximeter that uses six sets of light emitting diodes and photodetectors, uniformly distributed around the finger to identify the best signal path, thus making the signal acquisition immune to ring position. Moreover it uses a radio transceiver to eliminate the connection wires to a base station. In this proof of concept study, this novel ring oximeter was implemented with commercial low power consumption off-the-shelf components mounted on a rigid-flex board that connects to a remote host for signal processing and oxygen level calculation.

In this paper, we present a new dielectrophoretic microfluidic technique in a modular Lab-on-Chip (LoC) platform. The proposed LoC has a reconfigurable topology. It generates a wide range of signals depending on the analyzed liquid with a variable frequency up to 1.2 MHz. In addition, a programmable phase shift circuit with a minimum phase step of 3.6° for each signal is implemented. The amplitude of each signal can be adjusted independently, and the latter can be distributed through 64 bidirectional electrodes. Each electrode can be enabled or disabled individually. Moreover, device includes capacitive sensing stage for the measurement of the in-channel capacitance change induced by algae. Furthermore, The architecture of the proposed system is versatile and can be adjusted to different cell manipulation applications. The presented LoC was tested with 15 μm algae cells.

We present in this paper a new CMOS interface for cell manipulation by dielectrophoresis and capacitive sensing system dedicated for a lab-on-a-chip. It fully integrates a signal generation circuit and a post-processing system to control parameters of each signal such as frequency, phase and amplitude. In addition, a large capacitive and low resistive load driver circuit is designed to deliver a current of 9 mA for each 16 electrodes as the microfluidic architecture is divided into 4 blocs containing 16 electrodes each one. Thus, the proposed CMOS chip provides 4-channel signals with individually controllable phase and amplitude. In addition, a capacitive sensing system has been integrated into the same chip to detect the capacitive change in the microchannel in the Lab-on-a-chip. The generated signals have a 2.5 peak-to-peak voltage range and 70 kHz frequency range while the detection system has a dynamic range of 1.5 V and a sensitivity of 11.8 fF/V.