A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-VDDschemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-VDDscheme, respectively.

Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%.

In a conventional open bit-line scheme of DRAM, the edge subarrays (MATs) located at both ends of the cell array block contain alternated real and dummy bit-lines, unavoidably leading to an additional area overhead. To reduce the area overhead, one edge MAT can be eliminated by converting the dummy bit-lines of the other edge MAT into real bit-lines. This strategy causes the conventional bit-line sense amplifiers (BLSAs) in the MATs located at both ends of the cell array block to have a much smaller complementary bit-line capacitance than a true bit-line capacitance. Thus, the sensing operation of a conventional BLSA with this unbalanced bit-line capacitance experiences various problems: sensing voltage decrease, data flipping, and asymmetric equalization. To solve these problems, we propose a novel sensing circuit that can operate effectively even under unbalanced bit-line capacitance, thus suggesting the possibility of an open bit-line scheme without dummy bit-lines. Our proposed dummy-less open bit-line scheme can save approximately 4% of the array height. Compared with the conventional unbalanced BLSA, the proposed BLSA increases the sensing voltage by more than 100%, reduces the voltage peaks by 30% during the data transfer, and reduces equalization time by 1.2 ns in HSPICE Monte Carlo simulation.

Recently, with the increase in popularity of Internet of Things (IoT) devices, cryptographic protection techniques have become necessary for high-security applications. In general, IoT devices have strict power and area constraints. Thus, use of a physical unclonable function (PUF), which can generate a secret key at low cost, can be advantageous for high-security IoT devices. This paper presents a novel environmental-variation-tolerant (EVT) magnetic tunnel junction (MTJ)-based PUF that has a small area, high randomness, and low bit error rate (BER) compared to previous PUFs. The simulation results obtained using industry-compatible 65-nm model parameters indicate that the proposed PUF exhibits an inter-chip Hamming distance of 0.4901 and entropy of 0.9997, which proves the randomness of the PUF response. In addition, the proposed PUF exhibits the lowest BER across a wide voltage range (0.9 V-1.3 V) and temperature range (-25 °C - 75 °C) compared with previous PUFs.

In physically unclonable functions (PUFs), generating random cryptographs is required to secure private information. Various memory-based PUFs (MemPUFs), where cryptographs are generated independently from each PUF cell to increase the unpredictability of the cryptographs, have been proposed. Among them, the spin-transfer torque magnetic random-access memory MemPUF generates constant responses under temperature and voltage variations by exploiting a magnetic tunnel junction (MTJ) as the variation source. However, its response stability is diminished by the different characteristics of the two access transistors used in a PUF cell. To solve this problem, a novel PUF array that employs a diode-connected transistor and a shared access transistor, is proposed. In addition, a two-step postprocessing is adopted: 1) a write-back technique that amplifies the initial mismatch of MTJ resistances, and 2) a cell-classification technique that detects unstable PUF cells and discards their responses. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm technology show that the proposed PUF system achieves the highest independence (autocorrelation factor of 0.0306) and the lowest maximum bit error rate (BER) under temperature and supply-voltage variations (<; 0.01% and 0.04% in the ranges of -25 to 75 °C and 0.8-1.2 V, respectively) compared with conventional PUF systems that exploit independent variation sources.

In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%-48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10-4-10-2raw bit-error rate.

In the case of dynamic random access memory (DRAM) using a voltage latched sense amplifier, various offset voltage cancellation techniques have been studied to secure the sensing margin. However, as coupling noise and process variations increase with technology scaling, it is impossible to obtain a sufficient sensing margin only by using an offset voltage cancellation technique. In addition, offset voltage cancellation techniques have several problems, such as area overhead and sensing speed slowdown at a low supply voltage. In this paper, we propose a sense amplifier that maximizes the sensing margin by boosting the reference bitline voltage during the charge sharing operation and adopting the offset voltage cancellation technique. The sensing voltage difference of the proposed sense amplifier increases by 50% or more than that of the conventional offset cancellation (OC) sense amplifier at the low supply voltage of 0.9 V, which can improve not only the sensing speed by 2 ns but also the sensing yield by 11.8%. In addition, the proposed sense amplifier achieves a stable sensing yield with a larger cell array height and thus can compensate the area overhead of 44% caused by the OC technique by decreasing the overall cell array height.

In the design of nonvolatile memory (NVM), the sensing scheme (SS) has become a read-energy bottleneck because the required read-cell current is too large to satisfy a target read yield. This problem is further aggravated by technology scaling because increased process variation and reduced supply voltage (VDD) require more current to satisfy the target read yield. This paper proposes an offset-canceling single-ended SS (OCSE-SS) with one-bit-line precharge architecture (1BLPA) that is intended for use in ultralow power NVM applications. The test chip is fabricated using 65-nm process technology, and the measurement results show that the read energy per bit of the OCSE-SS is 1/3 compared to that of the conventional SS (Conv-SS). The read energy reduction comes from the singleended sensing, offset cancellation, and 1BLPA features. Moreover, when a resistance difference between the data and reference cells is as small as 0.5 kQ, the OCSE-SS reads successfully with a VDD of 1.0 V and a sensing time (tSEN) of 17 ns due to the offset cancellation characteristic, whereas the Conv-SS fails regardless of VDD and tSEN values.

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual Vrefsensing scheme (DVSS) that selectively uses an optimal Vrefbetween Vref+and Vref-is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal Vrefis selected after fabrication, and the calibrated switch control bit, which contains Vrefselection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with 2× faster sensing speed and 1.5× lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

A global reference-circuit (RC), which means one RC is shared with many sensing circuits (SC), is being considered for high-bandwidth STT-RAMs because of the low power consumption and small area characteristic. However, using the global RC for high-bandwidth STT-RAMs causes a droop effect and coupling noise effect, leading to the significant performance degradation. Thus, the validity of using the global RC should be identified. In this paper, the local RC and various global RCs are introduced, and compared in aspects of area, sensing time, and power consumption. By classification of the merits and demerits of various RCs, we present the following requirements of proper RC for high-bandwidth STT-RAMs: 1) small area, 2) no performance degradation, 3) low power consumption, and 4) process variation tolerant reference signal generation.