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Takumi Nito

dblp:164/5512 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 100%
Databases, data mining, and information retrieval
1 paper
Graph data management · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD
data allocation
0.312018
Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory · IEEE Trans. Computers 2018
Storage systems
flash and SSD
0.312018
Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory · IEEE Trans. Computers 2018
Storage systems › flash and SSD › flash memory management
garbage collection
0.312018
Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory · IEEE Trans. Computers 2018
Storage systems › flash and SSD › flash memory
NAND flash
0.312018
Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory · IEEE Trans. Computers 2018
Graph data management › graph analytics
large-scale graph analytics
0.112018
Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory · IEEE Trans. Computers 2018
YearPublicationVenuePosition
2018 Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory
abstract
A new control scheme for eliminating garbage collection during high-speed analysis of big-graph data stored in NAND flash memory is proposed and evaluated. During big-graph analysis, intermediate results of the analysis are stored in NAND flash memory and updated repeatedly. Under a conventional control scheme, excessive data copying, called “garbage collection,” occurs because overwriting data to NAND flash memory is prohibited. Such excessive data copying degrades performance of big-graph analysis. In contrast, under the proposed control scheme, the controller of NAND flash memory writes the intermediate results, which are updated at the same time, to the same block of NAND flash memory, and the excessive data copying is eliminated completely because all the data in the block can be erased at the same time before the intermediate results are updated. As a result, the proposed scheme shortens analysis time by 88 percent and increases analysis speed for big graphs 8.7 times. The proposed scheme can be applied to three-dimensional NAND flash memory and increases analysis speed 9.5 times. Also, the proposed scheme can be applied to an emerging high-density memory such as three-dimensional vertical chain-cell phase-change memory. These results show that the proposed control scheme enables high-speed analysis of big graphs.
Hiroshi Uchigaito, Seiji Miura, Takumi Nito
IEEE Trans. Computers3
2015 A control scheme for eliminating garbage collection during highspeed analysis of big-graph data stored in NAND flash memory
abstract
A new control scheme for eliminating garbage collection during high-speed analysis of big-graph data stored in NAND flash memory is proposed and evaluated. During big-graph analysis, intermediate results of the analysis stored in NAND flash memory are updated repeatedly. When a conventional control scheme is applied, excessive data copying, called “garbage collection,” occurs because overwriting data to NAND flash memory is prohibited. Such excessive data copying degrades the performance of big-graph analysis. When the proposed control scheme is applied, the controller of NAND flash memory writes the intermediate results which are updated at the same time to the same block of NAND flash memory, and the excessive data copying is eliminated completely because all the data in the block can be erased at the same time before the intermediate results are updated. As a result, the proposed control scheme shortens analysis time by 88% and increases analysis speed for big graphs 8.7 times. These results show that the proposed control scheme enables high-speed analysis of big graphs.
Hiroshi Uchigaito, Seiji Miura, Takumi Nito
ISCAS3