This paper describes a system that has been developed for automatically measuring the enhancement in the peak/rms ratio that a given audio processor provides, and gives some preliminary results on the performance of three commercial audio processors and two rather simple processors. An important outcome of the results is the establishment of an engineering goal for an improved digital signal processing (DSP) speech enhancement algorithm.

A novel technique for coping with fading and burst noise on HF channels used for digital voice communication has been developed and evaluated. The technique transmits digital voice only during the high signal-to-noise ratio time intervals, i.e., channel "on" times, and speeds up the speech when necessary in order to avoid delays which would hinder conversation. The technique was evaluated using a spoken version of a reading comprehension test. The test involved 15 spoken, 2-min paragraphs processed by a real-time channel vocoder simulation which had been modified to also simulate the on/ off characteristics of a fading HF channel. Based on informal listening tests, four test conditions were selected in order to characterize those conditions of interrupting the speech that would render it comprehensible or incomprehensible. One of the test conditions, 2 s on\frac{1}{2}s off on the average, produced percentage correct test scores comparable to the reference continuous speech case. Since this condition represents a reasonable match to the temporal variations of a disturbed ionosphere, and also represents a more difficult condition than the slower variations of an undisturbed ionosphere, it is concluded that the sped-up speech technique is appropriate for HF digital voice communication systems.

A comparative performance rating of circuit techniques for performing logical functions in digital systems may be based upon: 1) Reliability and simplicity 2) Input and output capabilities 3) Propagation time 4) Cost. The ``Hybrid Transistor Diode Logic'' (HTDL) circuit technique employs either diodes or emitter follower transistors as gates and buffers, to maximize the circuit performance rating. The HTDL technique thus combines the advantages of lumped and distributed gain circuits. The cascading of diodes and emitter followers in logical gate matrices can be analyzed as the transmission of binary signals through a video system of a given bandwidth. The HTDL technique optimizes the use of the transistor through nonsaturating, low-impedance circuitry. This optimum use of 200-500 megacycle gain-bandwidth transistors is primarily limited by present-day packaging techniques and their inductive and capacitive loading effects upon the circuits. The development of macromodule packaging techniques, using 200-500 mc transistors, in HTDL circuitry, would permit system speeds (synchronous clock rates) to exceed 50 Mc.