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Tohru Uchiyama

dblp:164/6865 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Routing and switching · 67% Internet architecture and protocols · 33%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Routing and switching › packet switching
high-speed packet switching
0.011987
High-Speed Packet Switching Systems for Multimedia Communications · IEEE J. Sel. Areas Commun. 1987
Routing and switching
packet switching
0.011987
High-Speed Packet Switching Systems for Multimedia Communications · IEEE J. Sel. Areas Commun. 1987
Internet architecture and protocols › protocol implementation
protocol processing
0.011987
High-Speed Packet Switching Systems for Multimedia Communications · IEEE J. Sel. Areas Commun. 1987
Interconnection networks and networks-on-chip › network topology
hierarchical interconnection network
0.011987
High-Speed Packet Switching Systems for Multimedia Communications · IEEE J. Sel. Areas Commun. 1987

Methods — techniques the papers use, named apart from their topics

parallel processing algorithm · 0.0distributed system architecture · 0.0
YearPublicationVenuePosition
1987 High-Speed Packet Switching Systems for Multimedia Communications
abstract
High-speed packet switching (HPS) systems can Provide flexible, economical, high-quaiity services for integrated voice, video, and data communications. To realize such HPS systems, methods have been developed to bring about high-speed protocol processing as well as a system architecture for facilitating high-throughput switching. Adopting the parallel processing algorithm into protocol processing allows us to achieve high-speed packet protocol processing of about 100 times faster than conventional processing. Furthermore, a fully distributed system architecture in addition to hierarchical interconnection networks can achieve high-capacity packet switching systems. The proposed HPS system is thus capable of accommodating lines of up to 10-50 Mbits/s, of providing high-throughput switching capability of 1 000 000 packets/s, and of having an average delay of less than 2 ms. Furthermore, an evaluation of network delay performances of video conferencing and voice communications indicate that HPS systems are quite suitable for handling such multimedia communications.
Hiroyuki Ichikawa, Makoto Aoki, Tohru Uchiyama
IEEE J. Sel. Areas Commun.3