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Sharanyan Srikanthan

dblp:164/8074 · DBLP profile ↗
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4ranked-venue papers
4as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 4 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Parallel and multicore computing · 33% Processor architecture and microarchitecture · 20% Cloud and datacenter computing · 18%
Software engineering, system software, and programming languages
1 paper
Operating systems · 100%

Topics — the 11 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management
0.612022
MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022
Embedded and real-time systems › real-time scheduling
quality-of-service-aware scheduling
0.612022
MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022
Parallel and multicore computing › parallel scheduling
runtime scheduling
0.612022
MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022
Processor architecture and microarchitecture
resource contention
0.322019
Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems · USENIX ATC 2015
Managing application parallelism via parallel efficiency regulation: poster · PPoPP 2019
Operating systems › resource management › process management
CPU scheduling
0.212016
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing · USENIX ATC 2016
Processor architecture and microarchitecture
chip multiprocessor
0.212015
Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems · USENIX ATC 2015
Performance modeling and evaluation › performance monitoring
hardware performance counters
0.212022
MAPPER: Managing Application Performance via Parallel Efficiency Regulation* · ACM Trans. Archit. Code Optim. 2022
Memory systems
cache coherence
0.112016
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing · USENIX ATC 2016
Processor architecture and microarchitecture
multicore design
0.112016
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing · USENIX ATC 2016
Distributed systems › resource sharing
data sharing
0.112015
Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems · USENIX ATC 2015
Parallel and multicore computing › parallel architecture
multicore performance
0.112015
Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems · USENIX ATC 2015

Methods — techniques the papers use, named apart from their topics

task-to-CPU placement · 0.6hardware performance counters · 0.6
YearPublicationVenuePosition
2022 MAPPER: Managing Application Performance via Parallel Efficiency Regulation*
abstract
State-of-the-art systems, whether in servers or desktops, provide ample computational and storage resources to allow multiple simultaneously executing potentially parallel applications. However, performance tends to be unpredictable, being a function of algorithmic design, resource allocation choices, and hardware resource limitations. In this article, we introduce MAPPER, a manager of application performance via parallel efficiency regulation. MAPPER uses a privileged daemon to monitor (using hardware performance counters) and coordinate all participating applications by making two coupled decisions: the degree of parallelism to allow each application to improve system efficiency while guaranteeing quality of service (QoS), and which specific CPU cores to schedule applications on. The QoS metric may be chosen by the application and could be in terms of execution time, throughput, or tail latency, relative to the maximum performance achievable on the machine. We demonstrate that using a normalized parallel efficiency metric allows comparison across and cooperation among applications to guarantee their required QoS. While MAPPER may be used without application or runtime modification, use of a simple interface to communicate application-level knowledge improves MAPPER’s efficacy. Using a QoS guarantee of 85% of the IPC achieved with a fair share of resources on the machine, MAPPER achieves up to 3.3 \( \times \) speedup relative to unmodified Linux and runtime systems, with an average improvement of 17% in our test cases. At the same time, MAPPER violates QoS for only 2% of the applications (compared to 23% for Linux), while placing much tighter bounds on the worst case. MAPPER relieves hardware bottlenecks via task-to-CPU placement and allocates more CPU contexts to applications that exhibit higher parallel efficiency while guaranteeing QoS, resulting in both individual application performance predictability and overall system efficiency.
Sharanyan Srikanthan, Sayak Chakraborti, Princeton Ferro, Sandhya Dwarkadas
ACM Trans. Archit. Code Optim.1
2019 Managing application parallelism via parallel efficiency regulation: poster
abstract
Modern multiprocessor systems contain a wealth of compute, memory, and communication network resources, such that multiple applications can often successfully execute on and compete for these resources. Unfortunately, good performance for individual applications in addition to achieving overall system efficiency proves a difficult task, especially for applications with low parallel efficiency (speedup per utilized computational core). Limitations to parallel efficiency arise out of factors such as algorithm design, excess synchronization, limitations in hardware resources, and sub-optimal task placement on CPUs.
Sharanyan Srikanthan, Princeton Ferro, Sayak Chakraborti, Sandhya Dwarkadas
PPoPP1
2016 Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing
Sharanyan Srikanthan, Sandhya Dwarkadas
USENIX ATC1
2015 Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems
Sharanyan Srikanthan, Sandhya Dwarkadas
USENIX ATC1