The increasing deployment of AI (artificial intelligence) on edge devices presents major challenges due to strict constraints on computation, memory, energy, and latency. Effective Edge AI systems thus require multi-objective optimization that balances accuracy, hardware efficiency, and reliability. The Horizon Twinning project AIDA4Edge tackles these challenges by developing methods for efficient and reliable AI on resource-constrained platforms. This paper presents key approaches explored within the project, including neural network quantization, hardware-aware neural architecture search, dynamic neural networks, and self-adaptive resilient AI architectures. Finally, these strategies are placed within a broader, biologically inspired paradigm, highlighting neuromorphic computing as a natural continuation of Edge AI efforts toward highly efficient and resilient intelligent systems.

This tutorial addresses the benefits one can take from deploying on-chip lifecycle management (OCLM) to design resilient Systems-in-Package (SiP). Such benefits are based on the massive deployment of on-chip cross-layer, collaborative sensors that are placed in strategic points of the chiplets and interposer, a data wrapper interface & management hub that is responsible to process and store the collected data from the sensors in a way to create an in-mission history of events, and on-chip analytics engine. The sensors can monitor from siliconlevel information (such as transistor aging, power-supply noise activity, electromigration, and transient faults in memory elements) up to system-level transactions in system bus, processor cores and memory IPs (e.g. task scheduling algorithm, and data and instructions fetched in memory). The sensors can be placed on dies on interposer. Furthermore, IEEE and IEC standards can be used to support data monitoring and collection processes. The analytics engine can be implemented based on simple/straightforward data structures such as Look-up Table (LUT) and Content-Addressable Memory (CAM), or be based on advanced Machine Learning/Artificial Intelligence (ML/AI) algorithms such as Dynamic Neural Network (DNN). The ultimate goal is to perform on-chip lifecycle management to trade, in-mission mode, power, performance, reliability and lifespan.

Reliable electronics plays a major role in shaping our daily lives, being a key enabler for critical applications, such as space missions, avionics, automotive, medicine, banking, automated industry, wireless communication networks, etc. However, design of highly reliable electronic systems remains a challenge with the advances in semiconductor technology and increase in integrated circuit (IC) complexity. In this work, we introduce the Horizon Europe Twinning project TWIN-RELECT, aimed at strengthening the scientific expertise in designing reliable integrated circuits. The paper presents the general project concept and objectives, and main directions of the joint research activities. The primary scientific goal is to contribute to the development of novel, more efficient, European Electronic Design Automation (EDA) tool-chain for design of reliable chips.

The growing demand for deployment of Artificial Intelligence (AI) on resource-constrained edge devices has motivated extensive research on the design of efficient edge-compatible AI hardware accelerators. One of the most promising solutions are the self-adaptive AI accelerators, capable of optimizing in real time their performance and energy consumption according to application requirements. This work introduces the EU-funded project Twinning for Excellence in Adaptive Edge Artificial Intelligence (AIDA4Edge), aimed to advance the state-of-the-art in the design of adaptive neural network accelerators for edge applications. The main goal is to develop a novel hybrid self-adaptive neural network architecture combining spiking and artificial neural networks, and supporting runtime adaptation of network functionality, precision and reliability. Furthermore, we aim to enhance the neural network training by incorporating hardware and quantization constraints in an automated tuning engine.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

The unified 3D communication networks, integrating standard terrestrial mobile communication networks and non-terrestrial networks (NTNs), are seen as the key enabler for global connectivity in the next generation (6G) wireless communications. To achieve this goal, new technologies and components are needed in order to meet the requirements for the 6G networks in terms of higher data rates, and enhanced reliability, security and network reconfigurability. This work introduces the German project 6G-TakeOff, aimed at the design of solutions for unified 3D networks for 6G wireless communication systems. The project consortium brings together academic and industrial partners from Germany and Europe, covering the entire value chain from design of electro-nics to applications. This work presents the key hardware components required for 3D networks and the concept for demonstration of their functionality.

Detection and measurement of ionizing radiation is required in a wide range of terrestrial applications, as well as in space missions. For this purpose, special instruments composed of radiation sensors and readout electronics are utilized. As ionizing radiation may affect the operation of electronic systems, radiation hardness is one of the main design requirements for radiation monitoring systems. In this work, we present a concept of a smart multi-sensor radiation monitoring system. The proposed design is based on the results achieved within the framework of EU-funded ELICSIR project. Our solution provides a new perspective on smart radiation monitoring by combining the concepts of self-awareness, self-adaptivity and artificial intelligence. This solution is suitable for applications where long-term autonomous radiation monitoring is required, such as environmental monitoring at terrestrial level or radiation monitoring in space missions.

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ($32.4\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$) to ($62.5\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$), depending on the variant.

Measurement of absorbed dose and dose rate is a common task in radiation environments such as space. This is accomplished with the specialized instruments known as radiation dosimeters. Among the most commonly used radiation dosimeters in space missions are those based on the Radiation Sensitive Field Effect Transistors (RADFETs). In this paper, we propose a design concept for a radiation hardened readout system for the real-time measurement of absorbed dose and dose rate with RADFET. The successive switching between the absorbed dose and dose rate readout modes, as well as the subsequent data processing, are performed by the self-adaptive fault-tolerant Multiprocessing System-on-Chip (MPSoC). The integrated framework controller and the real-time monitoring of particle flux with the embedded Static Random Access Memory (SRAM) enable the autonomous selection of operating and fault-tolerant modes, thus achieving the optimal performance under variable radiation conditions.

A robust design, which is one of the main requirements for space applications is always a tradeoff between power and area budget, speed requirement and the overall reliability. The occurrence of Single Event Effects (SEE) induced by energetic particle hits in the silicon leads to the insertion of additional replica logic at the design phase in order to tolerate Single Event Upsets (SEU) or Single Event Transients (SET). One of the most traditional circuit design technique is Triple Modular Redundancy (TMR). This paper presents a design concept for Radiation-Hardness-by-Design (RHBD) of TMR standard cell gates with local SET filter on the datapath, composed of True Single-Phase Clock (TSPC) flip-flops. The circuit architecture of the novel TSPC-ΔTMR flip-flops is discussed and compared to the baseline standard cell D-flip-flop. Analog simulations under various process, voltage, and temperature (PVT) conditions show an improvement by 50 % of the gate delay of the baseline TSPC flip-flop. Moreover, the proposed TSPC-ΔTMR gate candidate has a delay overhead of only 130ps under worst case condition compared to the classical unhardened D-latch-based reference flip-flop. Test vehicles for electrical measurements and radiation tests are implemented in 0.13 μm BiCMOS technology.

Recently the conservative space industry driven by the requirements of novel applications decided to introduce multiprocessor systems. Following the same line of motivation we introduce the PISA multiprocessor chip with improved power robustness for space applications which is successfully produced and tested in IHP 130 nm technology. The paper brings several novelties in respect to the current state-of-the-art. The chip uses the Waterbear framework in which the multiprocessor cores can be dynamically put in one of three different operating modes according to the current application requirements regarding performance, power consumption and fault tolerance. The chip has special power supply architecture with 13 power domains and Adaptive Voltage Scaling (AVS) mechanism based on voltage regulators which imposes a non-standard IC design flow. The measurement results showed that the power supply of the multiprocessor cores can be reduced from the nominal 1,2 V downto 0,82 V without compromising power integrity.

Cosmic radiation phenomena such as Solar Particle Events cause high radiation flux lasting from hours to days, thus increasing the probability of Single-Event Upsets (SEUs) for several orders of magnitude. In space applications it is necessary, therefore, to monitor the SEU rate in order to ensure timely detection of high radiation levels and efficient protection of radiation-sensitive circuits. This work proposes an approach combining the SEU monitoring and data storage functions in the same on-chip Static Random Access Memory (SRAM) module, with negligible cost and overheads compared to traditional stand-alone SEU monitors. Furthermore, it also enables the detection of permanent faults in SRAM. The proposed monitor is intended to be further integrated into a highly dependable and self-adaptive multiprocessing platform in which it will drive the selection of the multiprocessor operating modes. Thus, a dynamic trade-off between reliability, performance and power consumption in real-time can be achieved.

Single event transients (SETs) stand out as one of the major causes of soft errors in nanoscale CMOS integrated circuits. To reduce the need for exhaustive circuit simulations in the design of radiation-hard integrated circuits, the cost-effective approaches for characterization and modeling of SET generation effects in standard logic cells are required. In this work, a SPICE-based methodology for characterization of SET generation effects, employing two different SET current models, is presented. Based on the acquired simulation results, the empirical models for the two main SET generation metrics (SET critical charge and SET pulse width) are derived. The SET generation models and the respective model parameters are intended to be used as inputs for the higher-level analysis of SET effects in digital circuits designed with the characterized standard logic cells. By storing the model parameters for each gate in the look-up table, instead of storing the raw data obtained from SPICE simulations, the amount of characterization data can be significantly reduced, allowing to speed up the subsequent SET analysis of a complex circuit.

A radiation-hardness-by-design (RHBD) method for flip-flop single-event upsets (SEUs) mitigation is studied in this paper. This method applies a certain radiation hardened structure, e.g., the dual-interlocked storage cell (DICE), to implement one stage latch of a flip-flop while the SEUs protection for the other stage is realized by adjusting the clock duty cycle to shorten its hold state duration. Since the radiation hardening technique is used for only one stage latch, the overall area and power costs can be lowered. This technique is compatible with the automatic digital design flow and was implemented for an asynchronous first-in-first-out (FIFO) circuit as a case study in this paper.

The paper presents a strategy for mitigation of SETs on a data path using three-clock input TMR (Triple Modular Redundancy) flip-flop cells (φTMR approach) as an alternative to the widely used TMR approach with local delay filtering (ΔTMR). The proposed flow enables the use of the common clock tree skewing techniques and is fully compatible with the standard digital design flow. The φTMR architecture is presented, and a shift-register test circuit is implemented in 130nm BiCMOS technology to compare the φTMR with the ΔTMR. Obtained results have shown that the φTMR approach results in power savings of 25% compared to ΔTMR. Furthermore, the robustness is increased by reducing the peak currents about 60% for the clock network, and 20% for the total current when φTMR is selected.

This paper presents a critical charge model for estimating the SET and SEU robustness. The proposed model has been derived by analytic fitting of SPICE results, using a Muller C-element designed in 65 and 130 nm bulk CMOS technologies as the target device. The critical charge is expressed in terms of the size of C-element, size of load inverter, supply voltage and temperature, for constant timing parameters of the SET/SEU current pulse. The proposed model could be utilized to calculate the critical charge causing a SET, for both analyzed technologies, with the accuracy comparable to SPICE simulations. The critical charge for SEU was higher than for SET, but the dependencies obtained for SET response were qualitatively similar to those for SEU. This implies that the proposed critical charge model may be applicable for optimizing the SET/SEU robustness evaluation of the circuits involving the Muller C-element. Moreover, the model may also serve as a basis for evaluating the SET/SEU robustness of other standard cells and other technologies, and thus also for analysis of the SET/SEU robustness of complex circuits.

The cascaded asymmetrically sized inverters can be employed as pulse stretchers, for the measurement of very short single event transient (SET) pulse widths (<; 200 ps). This paper analyzes, through the circuit simulations, the effects of various design and operating parameters on the normal operation and SET robustness of a two-inverter pulse stretcher designed in 250 nm bulk CMOS technology. It was shown that the SET hardness of the pulse stretcher can be enhanced by upsizing all transistors in the pulse stretcher without changing the sizing ratio. The SET hardness can also be improved by upsizing the load, but this approach is less effective than the pulse stretcher upsizing. Both upsizing approaches have a negligible impact on the normal operation of the stretcher, i.e. output pulse width. In addition, the operation and SET robustness of the pulse stretcher can be influenced by the operating temperature and supply voltage variations, and these effects should be considered in the design process. Based on the acquired simulation results, a general approach for the design of a radiation hardened CMOS pulse stretcher has been proposed.

This paper presents a design of an on-chip single event transient (SET) pulse width measurement system. The proposed system has been designed and implemented in IHP's 250 nm bulk CMOS technology and is intended for evaluation of SET effects in standard digital library cells. It is composed of an inverter-based target circuit, a pulse stretcher and a processing unit for counting the SET pulses and measuring the SET pulse width. The realized system is based on the combination of best practices from various existing designs, and it has a fairly simple architecture capable to provide reliable SET characterization. It supports serial interfacing with the external data acquisition unit which transfers the acquired data to the personal computer. The preliminary evaluation through the circuit-level simulations has demonstrated that the proposed design can detect and measure the SET pulse widths from around 100 ps up to 3.5 ns, with the measurement resolution of approximately 100 ps.

The relation between amplitude and duration of the current pulse induced by a high energy ionizing particle has been proposed as a criterion for evaluating the SET and SEU robustness of integrated circuits. This criterion has advantage over the widely accepted critical charge concept in the sense that it is less dependent on the current pulse shape. However, to the best of our knowledge, there is no known report on the impact of design and operating parameters on the amplitude-duration criterion. The need for extensive circuit or device simulations to derive the amplitude-duration curves under varying design and operating parameters makes this approach very time-consuming. In that regard, this work proposes a method to establish the amplitude-duration criterion, with a limited number of circuit simulations, as a rational function in terms of the sizing factors of target and load gates and supply voltage. Initial evaluation on a simple circuit composed of two inverters, designed in 130 nm bulk CMOS technology, has shown that the proposed method provides the accuracy comparable to SPICE simulations.

This paper analyzes the single event transient (SET) response of a single event latchup (SEL) protection switch (SPS) designed in the 130 and 250 nm bulk CMOS technologies. The analysis has been conducted through the SPICE simulations, using the standard double exponential current source as the SET model. It has been confirmed that the 130 nm SPS cell is more susceptible to SETs than the 250 nm version, i.e. the 130 nm SPS cell has exhibited significantly lower critical charge. Based on the simulation results, an analytical model for estimating the critical charge in terms of the transistor size, number of load cells, and duration of the SET current pulse, has been derived. Use of the proposed critical charge model simplifies the analysis of the SPS cell's susceptibility to SETs for custom designs.

A single event latchup protection switch (SPS) has been developed in the IHP 250 nm bulk CMOS technology. The SPS has been designed as a standard library cell intended for implementation in the radiation-tolerant application specific integrated circuits (ASICs). It provides detection of single event latchup and subsequent shut-down of power supply to critical elements within the chip to restore the normal operation. However, the SPS cell might be also susceptible to single event transients. In that regard, this work presents the simulation-based analysis of the response of SPS cell in the case of single event transients. The dependence of the single event transient response with respect to the injected charge, supply voltage, load and sensing transistor's size has been analyzed.