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Kaiming Jiang

dblp:165/2504 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 61% GPUs and heterogeneous computing · 30% Processor architecture and microarchitecture · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
GPUs and heterogeneous computing
GPU architecture
0.212015
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs · ACM Trans. Archit. Code Optim. 2015
Energy-efficient computing › energy-efficient architecture
GPU energy reduction
0.212015
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs · ACM Trans. Archit. Code Optim. 2015
Energy-efficient computing
power gating
0.212015
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs · ACM Trans. Archit. Code Optim. 2015
Processor architecture and microarchitecture › front-end
instruction fetch and decode
0.112015
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs · ACM Trans. Archit. Code Optim. 2015

Methods — techniques the papers use, named apart from their topics

power gating · 0.2lockstep execution · 0.2buddy cluster grouping · 0.2
YearPublicationVenuePosition
2015 Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs
abstract
A modern general-purpose graphics processing unit (GPGPU) usually consists of multiple streaming multiprocessors (SMs), each having a pipeline that incorporates a group of threads executing a common instruction flow. Although SMs are designed to work independently, we observe that they tend to exhibit very similar behavior for many workloads. If multiple SMs can be grouped and work in the lock-step manner, it is possible to save energy by sharing the front-end units among multiple SMs, including the instruction fetch, decode, and schedule components. However, such sharing brings architectural challenges and sometime causes performance degradation. In this article, we show our design, implementation, and evaluation for such an architecture, which we call Buddy SM . Specifically, multiple SMs can be opportunistically grouped into a buddy cluster. One SM becomes the master, and the rest become the slaves. The front-end unit of the master works actively for itself as well as for the slaves, whereas the front-end logics of the slaves are power gated. For efficient flow control and program correctness, the proposed architecture can identify unfavorable conditions and ungroup the buddy cluster when necessary. We analyze various techniques to improve the performance and energy efficiency of Buddy SM. Detailed experiments manifest that 37.2% front-end and 7.5% total GPU energy reduction can be achieved.
Tao Zhang 0046, Naifeng Jing, Kaiming Jiang, Wei Shu, Min-You Wu, Xiaoyao Liang
ACM Trans. Archit. Code Optim.3