As an emerging role in new-generation on-chip communication, optical networks-on-chip (ONoCs) provide ultra-high bandwidth, low latency, and low power dissipation for data transfers. However, the thermo-optic effects of the photonic devices have a great impact on the operating performance and reliability of ONoCs, where the thermal-aware control with accurate measurements, e.g., thermal sensing, is typically applied to alleviate it. Besides, the temperature-sensitive ONoCs are prone to be attacked by the hardware Trojans (HTs) covertly embedded in the counterfeit integrated circuits (ICs) from the malicious third-party vendors, leading to performance degradation, denial-of-service (DoS), or even permanent damages. In this article, we focus on the tampering and snooping attacks during the thermal sensing via micro-ring resonator (MR) in ONoCs. Based on the provided workflow and attack model, a new structure of the anti-HT module is proposed to verify and protect the obtained data from the thermal sensor for attacks in its optical sampling and electronic transmission processes. In addition, we present the detection scheme based on the spiking neural networks (SNNs) to implement an accurate classification of the network security statuses for further high-level control. Evaluation results indicate that, with less than 1% extra area of a tile, our approach can significantly enhance the hardware security of thermal sensing for ONoC with trivial costs of up to 8.73%, 5.32%, and 6.14% in average latency, execution time, and energy consumption, respectively.

The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core interconnection architecture in recent years. However, the traditional electrical lines have very limited bandwidth and high energy consumption, making the photonic interconnection promising for future 3D Optical NoCs (ONoCs). Since existing solutions cannot well guarantee the fault-tolerant ability of 3D ONoCs, in this paper, we propose a reliable optical router (OR) structure which sacrifices less redundancy to obtain more restore paths. Moreover, by using our fault-tolerant routing algorithm, the restore path can be found inside the disabled OR under the deadlock-free condition, i.e., fault-node reuse. Experimental results show that the proposed approach outperforms the previous related works by maximum 81.1 percent and 33.0 percent on average for throughput performance under different synthetic and real traffic patterns. It can improve the system average optical signal to noise ratio (OSNR) performance by maximum 26.92 percent and 12.57 percent on average, and it can improve the average energy consumption performance by 0.3 percent to 15.2 percent under different topology types/sizes, failure rates, OR structures, and payload packet sizes.

Optical switching has been investigated for a long time, as a possible effective solution to overcome the limitations of power consumption, footprint and scalability in data center networks (DCNs). However, with the increasing DC traffic and narrow channel spacing between wavelengths for optical interconnects, traditional single-mode and multi-waveguide optical switching solutions have encountered bandwidth bottlenecks. To this end, we propose a 2×2 silicon-based on-chip optical switching architecture compatible with hybrid wavelength-andmode division multiplexing (WDM-MDM), and it is found experimentally that the proposed design increases the bandwidth 8× times with low crosstalk.

Nowadays, owing to the advantages of high bandwidth and low power consumption, the wired optical network-on-chip (W-ONoC) has emerged as a high-performance on-chip communication solution. However, the W-ONoC suffers from increased latency and limited scalability since the multi-hop data transmission is frequently performed in wired structures. In addition, several problems such as photoelectric conversion and thermal sensitivity pose challenges to the design of WONoCs. In this paper, we develop a novel on-chip communication architecture based on free-space optics (FSO), and leverage a suite of emerging devices. The proposed architecture eliminates the power loss caused by the waveguide and microring resonator previously deployed in W-ONoCs, and the transmission latency is also reduced through simplifying the packet switching. Moreover, compared with the traditional single-layer FSO NoC, our 3D FSO NoC further decreases the number of consumed lasers and power. Extensive simulation results demonstrate the aforementioned advantages of our solution.

In sharing economy, people offer idle social resources to others in a sharing manner. Through community-based online platforms, the people offering services can earn commission while others can enjoy a better life via renting social resources. Consequently, the value-in-use of services is expectedly strengthened within the unit time, although the total amount of social resources remains constant. Influenced by sharing economy, some famous companies have developed intelligent systems to analyze the most appropriate coincidence between citizens' idle supply and renting demand from numerous data sets. However, the big data analysis of the optimal service-demand matching usually runs on the traditional multiprocessors equipped in intelligent systems, so-called “system-on-chip.” In this paper, we design a novel computer architecture - the accelerator based on optical network-on-chip (ONoC) - to further speed up the matching between citizens' offer and demand in sharing economy. Our ONoC-based accelerator is able to quickly calculate the optimal service-demand matching by processing computation tasks on parallel cores, i.e., task-core mapping. In addition, to improve the accelerator reliability, the assorted task-core mapping algorithm is also designed. The extensive simulation results based on real trace file demonstrate the effectiveness of our system and algorithm. Note to Practitioners - Sharing economy is of great importance for realizing green consumption and sustainable development in our human society. Sharing economy enterprise calls for intelligent system design for service-demand matching in the current big data era. In this paper, we design the accelerator based on ONoC to further speed up the matching between citizens' offer and demand in sharing economy. By processing computation tasks on parallel cores using our algorithm, the task-core mapping can be performed with high speed and reliability. The simulation results - based on the trace file of Amazon Mechanical Turk - can well guide the practitioners to design a more clever and reliable product by quickly calculating the optimal service-demand matching.