Bhaskar Chaudhury

dblp:166/1454 · DBLP profile ↗
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12ranked-venue papers
1as first author
7since 2021 · last 2026
0000-0001-7618-3737ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 3 since 2021Artificial intelligence and machine learning · 3 · 2 since 2021Databases, data management, data science and information retrieval · 2 · 1 since 2021Theory of computation · 1Applied, interdisciplinary, general and emerging computing · 1
YearPublicationVenuePosition
2026 Physics guided Fourier Neural Operator framework for accelerated simulation of high power microwave breakdown
Kalp Pandya, Pratik Ghosh, Ajeya Mandikal, Shivam Gandha, Bhaskar Chaudhury
Eng. Appl. Artif. Intell.5
2024 CONCORD: enhancing COVID-19 research with weak-supervision based numerical claim extraction
Dhwanil Shah, Krish Shah, Manan Jagani, Agam Shah, Bhaskar Chaudhury
J. Intell. Inf. Syst.5
2023 Performance prediction from simulation systems to physical systems using machine learning with transfer learning and scaling
abstract
Summary Selection from several computer systems with different hardware features resulting in different software performance is a critical problem to solve. The problem becomes even more challenging when access to computer systems with different features is difficult. We had proposed a novel solution, “cross performance prediction with scaling,” in our previous work. In the scaling model, we predicted the physical system's runtime using a machine learning model trained only on a performance dataset of simulation‐based systems applying a scaling factor to the predicted runtime. In this article, we propose another novel idea, “cross performance prediction with transfer learning,” that uses transfer learning to solve the same problem. This model predicts the target physical system's performance using a machine learning model trained on a combined performance dataset from simulation‐based systems and an accessible source physical system. We evaluate both the models using several benchmark algorithms from SD‐VBS and MiBench suites. Our scaling model results have achieved a prediction error of 10%–25% for general‐purpose systems, whereas the transfer learning model has higher errors in the range of 50%. We have also developed a method to extract the rules built during the decision tree model's training to predict the runtime.
Amit Mankodi, Amit Bhatt, Bhaskar Chaudhury
Concurr. Comput. Pract. Exp.3
2022 An AutoML Based Algorithm for Performance Prediction in HPC Systems
Amit Mankodi, Amit Bhatt, Bhaskar Chaudhury
PDCAT3
2022 Parallel algorithm for synthetic image generation with application to tokamak plasma diagnostics
abstract
Summary The tomographic reconstruction is a powerful diagnostic tool in nuclear fusion experiments for the determination of the shape and position of the plasma. However, neural networks are emerging as a suitable alternative to conventional plasma tomography algorithms. In order to train such AI/ML based models, we need large‐scale, diversified image data for learning and evaluation which is difficult to obtain from real experiments. Accuracy and real‐time response is also critical, therefore in this article we propose an effective shared memory based parallel algorithm for synthetic imaging diagnostic data generation. The practicality of the proposed parallel algorithm has been evaluated experimentally by comparing it to the sequential algorithm on two different computing architectures. We observe a maximum speedup of 21 at 32 threads and demonstrate that our proposed parallel algorithm scales well over a range of image sizes. The proposed parallel algorithm can be used to obtain the synthetic images within a few seconds which is very important for real time applications. We also provide an analysis on the importance of choosing the right scheduling type and optimum chunk size to obtain the maximum speedup.
Kirtan Delwadia, Dhruvil Bhatt, Shishir Purohit, Bhaskar Chaudhury
Concurr. Comput. Pract. Exp.4
2021 Principal component analysis based construction and evaluation of cryptocurrency index
Agam Shah, Yagnesh Chauhan, Bhaskar Chaudhury
Expert Syst. Appl.3
2021 Parallel Fast Multipole Method accelerated FFT on HPC clusters
Chahak Mehta, Amarnath Karthi, Vishrut Jetly, Bhaskar Chaudhury
Parallel Comput.4
2020 Discovering Maximal Periodic-Frequent Patterns in Very Large Temporal Databases
abstract
Periodic-frequent pattern mining (PFPM) is an important data mining model having many real-world applications. However, the successful industrial application of this model has been hindered by the problem of combinatorial explosion of patterns, that is the generation of too many redundant patterns, most of which may be useless to the user. To address this problem, this paper proposes a novel model of maximal periodic- frequent pattern that may exist in a temporal database. A new pattern-growth algorithm, called Maximum Periodic-Frequent Pattern-growth (maxPFP-growth), has also been introduced to efficiently find all desired patterns in the data. Experimental results demonstrate that maxPFP-growth is not only memory and runtime efficient, but also highly scalable as well. The usefulness of our model has also been demonstrated with a case study on traffic congestion analytics.
R. Uday Kiran, Yutaka Watanobe, Bhaskar Chaudhury, Koji Zettsu, Masashi Toyoda, Masaru Kitsuregawa
DSAA3
2020 Multivariate Performance and Power Prediction of Algorithms on Simulation-Based Hardware Models
abstract
Power-aware computing has become increasingly important while considering the selection of computer systems to run the software. Several computer systems can have similar performance profiles with different power consumption for a given software. By accurately predicting the performance and power consumption of a software execution on different hardware systems, computer systems can be selected, which is a challenging problem. In this paper, we propose a novel multivariate prediction framework that predicts both performance and power consumption for a given software on unknown hardware identified by key hardware features. To measure the performance of our model, we have selected different software workloads according to their computation and memory access patterns consisting of kernels and benchmarks used in real-world applications. We have build 475 simulation-based hardware models with different instruction-set-architectures (ISAs) in the Gem5 simulator that represents computer systems of present times. We have trained our multivariate model on 60% of simulation-based hardware models, and the remaining 40% of hardware models used for prediction. Our result shows a prediction accuracy of greater than 95% for all the software workload for both performance and power consumption.
Amit Mankodi, Amit Bhatt, Bhaskar Chaudhury
ISPDC3
2020 Evaluation of Neural Network Models for Performance Prediction of Scientific Applications
abstract
Performance prediction is an important and active research area. In particular, several research efforts have built empirical models using machine learning algorithms for performance prediction. These models enable us to understand the dependence on hardware components for algorithm execution, system's scaling capabilities, cross-platform prediction in multi-core systems, and many others. The user community can use this knowledge to select hardware configurations best suited for executing a given software. In recent times, neural network-based models are widely used to build empirical models that understand complex relations between independent and dependent variables of an unknown data set. This paper has studied one-layer and multi-layer neural network models for performance prediction of three algorithms with different computations and memory-access patterns. We have shown that the multi-layer model outperforms the one-layer model, especially for computationally intensive algorithms. We have also shown that computationally intensive algorithms having a higher variance in runtime due to manufacturer variability require a higher number of neurons for convergence than memory-intensive algorithms. Our multi-layer neural network with optimal configuration has a prediction accuracy of about 88% for computationally intensive algorithms and about 95% for the memory-intensive algorithm.
Amit Mankodi, Amit Bhatt, Bhaskar Chaudhury
TENCON3
2018 Let's HPC: A web-based platform to aid parallel, distributed and high performance computing education
Bhaskar Chaudhury, Akshar Varma, Yashwant Keswani, Yashodhan Bhatnagar, Samarth Parikh
J. Parallel Distributed Comput.1
2017 A Novel Implementation of 2D3V Particle-in-Cell (PIC) Algorithm for Kepler GPU Architecture
abstract
The implementation of 2D-3v (2D in space and 3D in velocity space) PIC-MCC (Particle-In-Cell Monte Carlo Collision) method described in this paper involves the computational solution of Vlasov-Poisson equations, which provides the spatial and temporal evolution of the charged-particle velocity distribution functions in plasmas under the effect of self-consistent electromagnetic (EM) fields and collisions. Stringent numerical constraints associated with a PIC code makes it computationally prohibitive on CPUs in case of large problem sizes (total number of particles, number of grid points and simulation time-scale). We present the design and implementation of a Graphics Processing Unit (GPU) based 2D-3v PIC code using the CUDA C APIs for Kepler architecture. Several parallelization and optimization techniques have been presented in this paper with special emphasis on shuffle intrinsic specific to Nvidia Kepler architecture (or later), which significantly improves the performance compared to existing GPU implementations in the literature. On a test bed comprising of a serial implementation on Xeon E5 CPU and parallel implementations on Nvidia Tesla K40 graphics card, we have achieved a speedup of up to 60x in double precision mode. Effect of important numerical parameters on speedup has been investigated. Finally, we compare the performance of our best parallel implementation on different GPUs (Kepler as well as Maxwell) and analyze the effect of hardware architecture on the performance of the PIC code.
Harshil Shah, Siddharth Kamaria, Riddhesh Markandeya, Miral Shah, Bhaskar Chaudhury
HiPC5