Traditional digital implementations of neural accelerators are limited by high power consumption and area overheads, while analog and non-CMOS implementations suffer from noise, device mismatch, and reliability issues. This paper introduces a CMOS Look-Up Table (LUT)-based Architecture for Neural Accelerators (LANA) that reduces the power consumption and area overhead of traditional digital implementations through precomputed, faster LUT access while avoiding noise and mismatch challenges of analog circuits. To solve the scalability issues of conventional LUT-based computation, we split high-precision multiply and accumulate (MAC) operations into lower-precision MACs using a divide-and-conquer (D&C) based approach. LANA achieves up to 29.54× lower area with 3.34× lower energy per inference task compared to traditional LUT-based techniques and up to 1.24× lower area with 1.80× lower energy per inference task than conventional digital MAC-based techniques (Wallace Tree/Array Multipliers) without retraining and without affecting the accuracy of pre-trained unpruned models, as well as on Lottery Ticket Pruned (LTP) models that already reduce the number of required MAC operations by up to 98%. Finally, we introduce mixed precision analysis in the LANA framework for all LTP pruned and unpruned models (VGG11, VGG19, Resnet18, Resnet34, GoogleNet) that achieved up to 29.59× (GoogleNet pruned)-62.83× (VGG11 unpruned) lower area across models with 3.34× (GoogleNet pruned)-8.1× (VGG11 unpruned) lower energy per inference than traditional LUT-based techniques, and up to 1.24× (GoogleNet pruned)-2.63× (VGG11 unpruned) lower area requirement with 1.81× (GoogleNet pruned)-4.37× (VGG11 unpruned) lower energy per inference across models as compared to conventional digital MAC-based techniques with 1% accuracy loss relative to the baseline.

Physical unclonable functions (PUFs) are widely used for hardware security, yet conventional designs often suffer from considerable design overhead, limited placement flexibility, and susceptibility to environmental noise. This work presents DF-PUF, a dual-function, programmable entropy source tailored for secure and resource-efficient ASIC integration. DF-PUF leverages die-level process variations to generate device-unique responses for authentication, while its hardware resources can be dynamically repurposed as memory elements for local data storage when not operating as a PUF, thereby enhancing area efficiency. The architecture supports flexible deployment across the chip layout, facilitating integration in diverse design scenarios. Additionally, DF-PUF incorporates a noise-resilient response conditioning mechanism that mitigates environmental fluctuations, ensuring that output characteristics are predominantly determined by intrinsic process variations. These capabilities are achieved with minimal overhead, making DF-PUF a practical and scalable solution for secure embedded systems. Comprehensive evaluation through circuit-level simulations and silicon measurements on 65nm CMOS test chips demonstrates the proposed design’s superior uniqueness, randomness, and robustness.

Continuous remote monitoring of implantable medical devices, such as pacemakers, is limited by the high power consumption and security concerns of traditional wireless technologies like Bluetooth. In this work, we investigate Electro-Quasistatic Human Body Communication (EQS-HBC) as an alternative, leveraging the body itself as a communication channel between implants and wearable devices. EQS-HBC achieves real-time, high-throughput data transmission at power levels approximately 100 times lower than Bluetooth, enabling millisecond-resolution monitoring with minimal impact on device longevity. Through system-level optimization of sensing, memory, and communication, we demonstrate that EQS-HBC can support high temporal-resolution, secure data exchange without the high battery life penalties of current Radio-Frequency (RF) based solutions. These results highlight EQS-HBC's potential to transform remote care for patients by making truly continuous, personalized monitoring feasible.

In the rapidly evolving landscape of connected healthcare, this work offers new insights into self-powered, intelligent bio-electronics within the Internet of Bodies (IoB). Key prevailing challenges include the need for battery-free, wirelessly powered biomedical implants and efficient energy-harvesting (EH) methods that can sustain sensing, communication, and security functions in the complex tissue environment. Our proposed system utilizes a body-coupled powering (BCP) approach, harnessing the body’s natural conductive properties and employing galvanic coupling (G-BCP). By improving targeting accuracy, power transfer efficiency (PTE), and tissue penetration, G-BCP surpasses traditional wireless power transfer (WPT) methods. Additionally, a reconfigurable N-stage rectifier circuit enables maximum power transfer, adapting to frequency-dependent tissue-electrode impedance variations without any adaptive matching network. To substantiate the proposed design concept, a simulated prototype in Ansys HFSS, modeling a multi-layered tissue medium of 75 mm radius with a 5 mm implant depth, achieves over 11.7% peak PTE at 1 GHz and > 1 mW power delivery with a SAR limit of < 0.048W/kg from 0.78 - 1.35 GHz frequency range. Circuit-level simulations using the TSMC 65-nm CMOS process further confirm the system’s adaptability, with a 100-stage EH circuit reconfiguring to N < 100 for optimum WPT. Therefore, the G-BCP-based reconfigurable EH system is envisaged to be a key enabler in establishing a scalable framework for powering bio-implants in the realm of IoB applications.

Compute-in-memory (CiM) has emerged as a promising approach for improving energy efficiency for diverse data-intensive applications. In this paper, we present LUNA-CiM, a lookup table (LUT)-based programmable fabric for flexible and efficient mapping of artificial neural network (ANN) in memory. Its objective is to tackle scalability challenges in LUT-based computation by minimizing hardware, storage elements, and energy consumption. The proposed method utilizes the divide and conquer (D&C) strategy to enhance the scalability of LUT-based computation. For example, in a 4b × 4b lookup table-based multiplier, as one of the main components in ANN, decomposing high-precision operations into lower-precision counterparts leads to a substantial reduction in area overheads, approximately 73% less compared to conventional LUT-based approaches. Importantly, this efficiency gain is achieved without compromising accuracy. Extensive simulations were conducted to validate the performance of the proposed method. The analysis presented in this paper reveals a noteworthy advancement in energy efficiency, indicating a 58% reduction in energy consumption per computation compared to the conventional lookup table approach. Additionally, the introduced approach demonstrates a 36% improvement in speed over the traditional lookup table approach. These findings highlight notable advancements in performance, showcasing the potential of this inventive method to achieve low power, low-area overhead, and fast computations through the utilization of LUTs within an SRAM array.

A major challenge of long-term clock stability is frequency drift due to temperature variations. This paper describes the design of a proportional, integral, derivative (PID) control system for external ovenization of an AlScN-on-Si Shear-BAW Resonator (S3R), which has a fixed turnover temperature where the$1{^{\text {st}}}$order temperature coefficient of frequency is$\approx 0$ppm/°C. The control system provides$\pm ~0.125^{\circ }$C temperature stability and assists in achieving better than$\pm ~25$ppb frequency stability over a temperature range of 15-40°C by maintaining resonator operation near the turnover temperature, where the$2{^{\text {nd}}}$order temperature coefficient of frequency drift is -62.71ppb/°C2. The robust and adaptive PID algorithm (programmed on an external microcontroller unit connected to the interposer) ensures continuous ovenization by configuring the duty cycle of a compact heat actuator (powerMOS) that is placed in$\times 2$mm resonator and a complementary to absolute temperature sensor (implemented as a 1mm$\times 1$mm, 65nm integrated circuit), that are all held on a thermally conductive 7mm$\times$7mm Si interposer.

This paper presents a new analytical design technique to implement a generic, highly efficient, non-radiative inductive coupling (NRIC) system with maximum biomedical wireless power transfer (BWPT) capability and area control-lability. To achieve this, the configuration of the NRIC link comprises two planar spiral coils and two L-section impedance matching networks (IMN). A comprehensive theoretical analysis is conducted to arrive at a set of completely new and rigorous design equations utilizing the unique power transmission efficiency (PTE) vs frequency behavior for any system of 2-coils. The dependence of PTE on the coil area is also explored. Further, the corresponding S-parameters equations are derived, which determine the optimum PTE. To validate the proposed design concept, a prototype working at 20MHz is simulated, incorporating the human body tissue as the power transfer medium. This EM-simulated prototype laden with the IMNs exhibits excellent agreement with the theoretical aspects. Hence, the proposed design approach is envisaged to be an effective guideline in the realm of NRIC system design that will pave the way to implement the targeted BWPT.

Stochastic variation of process parameters within a die and technology-limitation-driven variation from die-to-die give rise to unique distribution patterns for manufacturing process parameters. These patterns work as a process signature that is transferred from the device level to the system level through electrical circuits and can be used to make a distinction among the processes. In this work, we propose an in-situ manufacturing process technology distinction method, radio frequency process specific functions (RF-PSFs), that uses process-specific inherent properties of an IC manifested in the transmitted radio frequency signal. Among many desirable testing criteria, RF-PSF addresses the question of fabrication with the intended process technology. This information plays an important role in modern zero-trust architecture and IC clone detection, a counterfeiting method where the IC is manufactured using a different process. An RF transmitter with RF-DAC power amplifier for QPSK modulation has been designed and simulated in 14, 22, and 65 nm processes for five process corners (TT, FF, FS, SF, and SS) in Cadence. The simulated data have been processed in MATLAB. A multilayer perceptron (MLP), trained with the constellation data, provides an average accuracy of${\sim }90\%$for process distinction. Realizing that: 1) a higher order modulation will have even more process information and 2) we can harness the convolutional neural network’s (CNNs) improved capability on pattern recognition, we can feed image-like constellation plots to a CNN to get better and consistent performance. Using the baseband constellations for 64-QAM modulated data as images, we have achieved${\sim }100\%$accuracy with commonly used, pretrained CNN models (ResNet18, ResNet50, and GoogleNet) through transfer learning. The separation among five process corners within a process, termed intraprocess variation, is also analyzed. The effect of baseband sampling rate and ADC resolution, two practical limitations in RF systems, have been explored. An extensive study has been performed on the effect of a key design parameter at the RF circuit level, i.e., W/L or aspect ratio, leading to design insights, proper CNN selection, and some control parameters. This work establishes RF-PSF as a zero-power, zero-area overhead, and in-situ process distinction method.

This work presents an interference-adaptive Gallium Nitride (GaN) low-noise amplifier (LNA) front-end with orthogonal frequency and linearity tuning for applications in communication base stations, radar and electronic warfare (EW). The system operates between 2–6 GHz and provides a sub 5 ms tuning time for an input power tuning range of 40 dB. The orthogonal tuning consists of two phases: 1. frequency tuning with four tunable bandpass and bandstop filters for interference rejection, 2. linearity tuning with a combination of coarse tuning through look-up table (LUT) and fine-tuning through incremental adaptation to trade off power with linearity. GaN LNA’s linearity can be adjusted between P textsubscript 1dB,IN = -10 and 1.5 dBm with output P textsubscript 1dB up to 25 dBm (11.5 dB range) with the LNA power changing from 500 mW to 2 W (x4 increase). The average LNA power with orthogonal frequency and linearity tuning decreases by 56% as compared with the system operating at the worst-case no tuning condition. Two systems involving commercial filters and custom cavity resonator-based filters were constructed. The filters further increase the system P textsubscript 1dB,IN by the filter rejection of the interference signal. The rest of the controls consume about 10% of the worst-case condition LNA power.

Intensive research on energy-harvested sensor nodes has been driven by the challenges in achieving stringent design goals of battery lifetime, information accuracy, transmission distance, and cost. This challenge is further amplified by the inherent power-intensive nature of long-range communication when sensor networks are required to span vast areas, such as agricultural fields and remote terrain. Solar power is a common energy source in wireless sensor nodes, however, it is not reliable due to fluctuations in available power stemming from the changing seasons and weather conditions. This article tackles these issues by presenting a perpetually powered, energy-harvesting sensor node which utilizes a minimally sized solar cell and is capable of long-range communication by dynamically co-optimizing energy consumption and information transfer, termed as energy-information dynamic co-optimization (EICO). This energy-information intelligence is achieved by adaptive dutycycling of information transfer based on the total amount of energy available from the harvester and charge storage element to optimize the energy consumption of the sensor node, while employing in-sensor analytics (ISA) to minimize loss of information. This is the first reported sensor node1 km at continuous information transfer rates of up to 1 packet/second which is enabled by EICO and ISA.

This work presents a white-box modeling of the electromagnetic (EM) leakage from an integrated circuit (IC) to develop EM side-channel analysis (SCA)-aware design techniques. A new digital library cell layout design technique is proposed to minimize the EM leakage and is evaluated using a high-frequency structure simulator (HFSS)-based framework. Backed by our physics-based understanding of EM radiation, the proposed double-row power grid-based digital cell layout design shows$>5\times $reduction in the EM SCA leakage compared to the traditional digital logic gate layout design. Furthermore, exploiting the magneto-quasistatic (MQS) regime of operation of the EM leakage from the CMOS circuits, the HFSS-based framework is utilized to develop a pre-silicon (Si) EM SCA evaluation technique to assess the vulnerability of cryptographic implementations against such attacks during the design phase itself.

Neuromorphic Computing has become tremendously popular due to its ability to solve certain classes of learning tasks better than traditional von-Neumann computers. Data-intensive classification and pattern recognition problems have been of special interest to Neuromorphic Engineers, as these problems present complex use-cases for Deep Neural Networks (DNNs) which are motivated from the architecture of the human brain, and employ densely connected neurons and synapses organized in a hierarchical manner. However, as these systems become larger in order to handle an increasing amount of data and higher dimensionality of features, the designs often become connectivity constrained. To solve this, the computation is divided into multiple cores/islands, called processing engines (PEs). Today, the communication among these PEs are carried out through a power-hungry network-on-chip (NoC), and hence the optimal distribution of these islands along with energy-efficient compute and communication strategies become extremely important in reducing the overall energy of the neuromorphic computer, which is currently orders of magnitude higher than the biological human brain. In this paper, we extensively analyze the choice of the size of the islands based on mixed-signal neurons/synapses for 3-8 bit-resolution within allowable ranges for system-level classification error, determined by the analog non-idealities (noise and mismatch) in the neurons, and propose strategies involving local and global communication for reduction of the system-level energy consumption. AC-coupled mixed-signal neurons are shown to have 10X lower non-idealities than DC-coupled ones, while the choice of number of islands are shown to be a function of the network, constrained by the analog to digital conversion (or viceversa) power at the interface of the islands. The maximum number of layers in an island is analyzed and a global bus-based sparse connectivity is proposed, which consumes orders of magnitude lower power than the competing powerline communication techniques.

Over the last decade, the growing influence of open source software has necessitated the need to reduce the abstraction levels in hardware design. Open source hardware significantly reduces the development time, increasing the probability of first-pass success and enable developers to optimize software solutions based on hardware features, thereby reducing the design costs. The recent introduction of open source Process Development Kit (OpenPDK) by Skywater technologies in June 2020 has eliminated the barriers to Application-Specific Integrated Circuit (ASIC) design, which is otherwise considered expensive and not easily accessible. The OpenPDK is the first concrete step towards achieving the goal of open source circuit blocks that can be imported to reuse and modify in ASIC design. With process technologies scaling down for better performance, the need for entirely digital designs, which can be synthesized in any standard Automatic Place-and-Route (APR) tool, has increased considerably, for mapping physical design to the new process technology. This work presents a first open source all-digital Serializer/Deserializer (SerDes) for multi-GHz serial links designed using Skywater OpenPDK 130nm process node. To ensure that the design is fully synthesizable, the SerDes uses CMOS inverter based drivers at the transmitter, while the receiver front end comprises a resistive feedback inverter as a sensing element, followed by sampling elements. A fully digital oversampling CDR at the receiver end recovers the transmitter clock for proper decoding of data bits. The physical design flow utilizes OpenLANE, which is an open source end-to-end tool for generating GDS from RTL. Cadence Virtuoso has been used for extracting parasitics for post-layout simulations, which exhibit the SerDes functionality at 2 Gbps for 34 dB channel loss while consuming 438 mW power. The generated GDS and netlist files of the SerDes, along with the required documentation, are uploaded in a GitHub repository for public access.

Unlike traditional radio frequency device authentication which utilizes security keys in conjunction with a digital subsystem for verification, human voice communication involves probabilistic identification of a person based on his/her voice signatures and improves the detection probability over time. Inspired by voice-based human identification, we implement a novel method of augmenting trust during device detection and authentication, involving dynamic irregular clustering which exploits the unique nonidealities in IoT devices as physical signatures originated from Radio Frequency (RF) circuitry. The proposed method increases the confidence level of the classification as more data come in from a particular device, and is also able to detect new devices that do not fall into any of the previous clusters. Using 30 Xbee modules as transmitters, we show that our proposed method can detect a transmitter with > 95% sensitivity 100% with optimum parameters) using only 0.2 milliseconds of test data which makes it suitable for a very low latency communication system. Also, the incremental learning feature of the proposed method renders a gradual increase in sensitivity as more data are available from the transmitter end. The proposed method can provide an additional security layer in conjunction with the existing methods without adding any additional burden, which is extremely important for resource-limited asymmetric IoT nodes.

In this paper, we present the design considerations for a sub-25μW phase-locked loop (PLL) with a wide tuning range and multi-phase outputs, which makes it suitable for applications that involve clock-and-data-recovery with variable data rates, such as broadband body-area-networks. Several architectures for the voltage- controlled-oscillator (VCO) are analyzed for power and performance, and the considerations for keeping the VCO's low-dropout-regulator (LDO) within the loop and outside the loop are discussed. Power consumption is minimized by keeping the LDO outside the loop, which exempts the error-amplifier (EA) from the bandwidth constraints posed by the PLL. Conforming to the analysis, the PLL is designed and simulated in a standard 65nm CMOS process, and the results show that energy-efficiencies as low as 70fJ/cycle can be achieved with a tuning range of 1-450MHz along with multi-phase outputs with RMS timing jitter of 11.4ps (frequency offset <; 100ppm) from a 31-stage split-tuned ring oscillator VCO.

Electromagnetic (EM) side-channel analysis (SCA) attack, which breaks cryptographic implementations, has become a major concern in the design of circuits and systems. This paper presents the design and analysis of the EM side-channel attack detection system utilizing patterned-ground co-planar capacitive asymmetry sensing (PG-CAS) for approaching probe, targeting to improve sensitivity, detection range, and power consumption compared to LC oscillator utilizing inductive sensing. The PG-CAS consists of a grid of four metal plates of the same size at the top metal layer and a patterned ground plane at a lower metal. As an EM probe approaches, electric field lines between the plates and plate-ground get distorted, thereby breaking the symmetry of the inter-plate and the plate-ground capacitance system and this change in capacitance is sensed. The PG-CAS circuit consists of two LC oscillators, mixer, low pass filter (LPF), resistive feedback amplifier (RFA) and a digital logic. By down-converting sensing signal to low-frequency using mixer, LPF, RFA and digital logic, the detection range is significantly improved. At a distance of 1 mm between the sensing metal plates and the approaching EM probe, system-level simulation results using TSMC 65nm technology and Ansys Maxwell show a > 10% change in the output frequency from the baseline frequency, leading to a > 10× improvement in the detection range and a ~ 3× improvement in power consumption over existing inductive sensing methods.

Decades of continuous scaling has reduced the energy of unit computing to virtually zero, while energy-efficient communication has remained the primary bottleneck in achieving fully energy-autonomous Internet-of-Things (IoT) nodes. This article presents and analyzes the tradeoffs between the energies required for communication and computation in a wireless sensor network, deployed in a mesh architecture over a 2400-acre university campus, and is targeted toward multisensor measurement of temperature, humidity and water nitrate concentration for smart agriculture. Several scenarios involving in-sensor analytics (ISA), collaborative intelligence (CI), and context-aware switching (CAS) of the cluster head during CI has been considered. A real-time co-optimization algorithm has been developed for minimizing the energy consumption in the network, hence maximizing the overall battery lifetime. Measurement results show that the proposed ISA consumes ≈ 467× lower energy as compared to traditional Bluetooth low energy (BLE) communication, and ≈ 69500× lower energy as compared with long-range (LoRa) communication. When the ISA is implemented in conjunction with LoRa, the lifetime of the node increases from a mere 4.3 h to 66.6 days with a 230-mAh coin cell battery, while preserving >99% of the total information. The CI and CAS algorithms help in extending the worst case node lifetime by an additional 50%, thereby exhibiting an overall network lifetime of ≈ 104 days, which is >90% of the theoretical limits as posed by the leakage current present in the system, while effectively transferring information sampled every second. A Web-based monitoring system was developed to continuously archive the measured data, and for reporting real-time anomalies.

Communication during touch provides a seamless and natural way of interaction between humans and ambient intelligence. Current techniques that couple wireless transmission with touch detection suffer from the problem of selectivity and security, i.e., they cannot ensure communication only through direct touch and not through close proximity. We present BodyWire-HCI , which utilizes the human body as a wire-like communication channel, to enable human–computer interaction, that for the first time, demonstrates selective and physically secure communication strictly during touch. The signal leakage out of the body is minimized by utilizing a novel, low frequency Electro-QuasiStatic Human Body Communication (EQS-HBC) technique that enables interaction strictly when there is a conductive communication path between the transmitter and receiver through the human body. Design techniques such as capacitive termination and voltage mode operation are used to minimize the human body channel loss to operate at low frequencies and enable EQS-HBC. The demonstrations highlight the impact of BodyWire-HCI in enabling new human–machine interaction modalities for variety of application scenarios such as secure authentication (e.g., opening a door and pairing a smart device) and information exchange (e.g., payment, image, medical data, and personal profile transfer) through touch (https://www.youtube.com/watch?v=Uwrig2XQIH8).

Traditional authentication in radio-frequency (RF) systems enable secure data communication within a network through techniques such as digital signatures and hash-based message authentication codes (HMAC), which suffer from key-recovery attacks. State-of-the-art Internet of Things networks such as Nest also use open authentication (OAuth 2.0) protocols that are vulnerable to cross-site-recovery forgery (CSRF), which shows that these techniques may not prevent an adversary from copying or modeling the secret IDs or encryption keys using invasive, side channel, learning or software attacks. Physical unclonable functions (PUFs), on the other hand, can exploit manufacturing process variations to uniquely identify silicon chips which makes a PUF-based system extremely robust and secure at low cost, as it is practically impossible to replicate the same silicon characteristics across dies. Taking inspiration from human communication, which utilizes inherent variations in the voice signatures to identify a certain speaker, we present RF-PUF: a deep neural network-based framework that allows real-time authentication of wireless nodes, using the effects of inherent process variation on RF properties of the wireless transmitters (Tx), detected through in-situ machine learning at the receiver (Rx) end. The proposed method utilizes the already-existing asymmetric RF communication framework and does not require any additional circuitry for PUF generation or feature extraction. The burden of device identification is completely shifted to the gateway Rx, similar to the operation of a human listener's brain. Simulation results involving the process variations in a standard 65-nm technology node, and features such as local oscillator offset and I-Q imbalance detected with a neural network having 50 neurons in the hidden layer indicate that the framework can distinguish up to 4800 Tx(s) with an accuracy of 99.9% [≈99% for 10000 Tx(s)] under varying channel conditions, and without the need for traditional preambles. The proposed scheme can be used as a stand-alone security feature, or as a part of traditional multifactor authentication.

Neuromorphic computing, inspired by the brain, promises extreme efficiency for certain classes of learning tasks, such as classification and pattern recognition. The performance and power consumption of neuromorphic computing depend heavily on the choice of the neuron architecture. Digital neurons (Dig-N) are conventionally known to be accurate and efficient at high speed while suffering from high leakage currents from a large number of transistors in a large design. On the other hand, analog/mixed-signal neurons (MS-Ns) are prone to noise, variability, and mismatch but can lead to extremely lowpower designs. In this paper, we will analyze, compare, and contrast existing neuron architectures with a proposed MS-N in terms of performance, power, and noise, thereby demonstrating the applicability of the proposed MS-N for achieving extreme energy efficiency (femtojoule/multiply and accumulate or less). The proposed MS-N is implemented in 65-nm CMOS technology and exhibits >100× better energy efficiency across all frequencies over two traditional Dig-Ns synthesized in the same technology node. We also demonstrate that the inherent error resiliency of a fully connected or even convolutional neural network can handle the noise as well as the manufacturing nonidealities of the MS-N up to certain degrees. Notably, a system-level implementation on CIFAR-10 data set exhibits a worst case increase in classification error by 2.1% when the integrated noise power in the bandwidth is ~ 0.1 μ V2, along with ±3σ amount of variation and mismatch introduced in the transistor parameters for the proposed neuron with 8-bit precision.

This paper presents a low-power integrated wireless telemetry system (Bio-WiTel) for healthcare applications in 401-406 MHz frequency band of medical device radiocommunication (MedRadio) spectrum. In this paper, necessary design considerations for telemetry system for short-range (upto 3 m) communication of biosignals are presented. These considerations help greatly in making important design decisions, which eventually lead to a simple, low power, robust, and reliable wireless system implementation. Transmitter (TX) and receiver (RX) of Bio-WiTel system have been fabricated in 180 nm mixed mode CMOS technology. While radiating -18 dBm output power to a 50 antenna, the packaged TX IC consumes 250 μW power in 100% on state from 1 V supply, whereas the RX IC consumes 990 μW power from 1.8 V supply with a sensitivity of -75 dBm. Measurement results show that TX fulfils the spectral mask requirement at a maximum data rate of 72 kb/s. The measured bit error rate (BER) of RX is less than for a data rate of 200 kb/s. The proposed Bio-WiTel system is tested successfully in home and hospital environments for the communication of electrocardiogram and photoplethysmogram signals at a data rate of 57.6 kb/s with a measured BER of <10 for a maximum distance of 3 m.

A novel receiver front-end is proposed for FM/FSK modulated signal, which is transmitted from a body worn device in the MedRadio spectrum of 401–406 MHz. The front-end comprises a low noise amplifier (LNA), a zero crossing detector (ZCD) and a frequency to digital converter (FDC). The proposed architecture offers direct digitization of the input signal and is immune to LO leakage and problem of image frequencies. Designed in 180 nm mixed mode CMOS technology, the worst case post layout simulation results show a sensitivity of −80 dBm at 200 kbps for FSK modulated input with only 990 μW power consumption.