This paper presents a compact, low-power analog front-end (AFE) for high-density micro-electrocorticography (μECoG) recordings. The AFE integrates a DC-coupled, chopper-stabilized low-noise boxcar sampler, a passive switched-capacitor low-pass filter, and a 10-bit single-slope analog-to-digital converter (ADC). The boxcar sampler minimizes noise folding, enhances anti-aliasing and reduces chopping ripple. To prevent AFE saturation, a novel electrode DC offset (EDO) compensation loop is introduced. It features an embedded digital-to-analog converter (DAC) by modulating the bulk terminals of the input transistors, and a bi-level compensation scheme, thereby eliminating the requirements for high-resolution digital low-pass filters and explicit DACs typically used in traditional DC servo loops. Simulation results in 40nm bulk CMOS show an input-referred noise of 1.69 μVrmsover a 1-500 Hz bandwidth, an EDO compensation range of 110 mVpp, with a power consumption of 2.28 μW and an estimated area of 0.0028 mm2per channel.

A single transmitter source can power multiple ultrasound piezoelectric transducers to enhance the harvested power; however, the received ultrasonic signals vary in phase and amplitude across each element. This paper introduces a fully integrated, high-frequency SSHC rectifier tailored for miniaturized multi-piezo implants to efficiently harvest power at variable phase offsets with a compact form factor. The design incorporates a novel phase-splicing flipping capacitor-sharing technique between all four ultrasound piezoelectric transducers to improve area efficiency. The proposed 4-stage SSHC rectifier can harvest 5.94x more power than a full bridge rectifier operating at a high ultrasonic excitation frequency of 780 kHz. The proposed system was designed using 180-nm BCD process technology for a 2x2 piezoelectric transducer array, with each element featuring an internal capacitor (CP) of 63.7pF.

Power and area efficient on-chip feature extraction is needed for future closed-loop neural interfaces. This paper presents a feature extraction unit for neural oscillatory synchrony that bypasses the phase extraction step to reduce hardware complexity. Instead, the sine and cosine of the phase are directly approximated from the real and imaginary components of the signal to calculate the phase-amplitude coupling (PAC) and phase locking value (PLV). The synthesized design achieves state-of-the-art performances at 43 nW/channel and 0.006 mm2, while maintaining sufficient accuracy for seizure detection in epileptic patients.

This paper introduces a fast artifact recovery algorithm (FARA) that uses electrochemical impedance spectroscopy to model the electrode-tissue interface and design an optimum stimulation waveform to minimize the residual artifact duration in single-cell resolution neural interfaces. Results in saline solution with a custom PCB and a 30 $\mu \mathrm{m}$ diameter microelectrode array show a worst case artifact recovery time of 160 $\mu \mathrm{s}$ when measured from the end of the working phase (anodic 500 $\mathrm{n}\mathrm{A}, 250\mu \mathrm{s})$. On average, the proposed algorithm provides an 81% improvement over a triphasic charge-balanced stimulation waveform.

This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit's unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately 2× and 10×, respectively. The 1.44 mm2chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature.

Current retinal prostheses provide electrical stimulation without feedback from the stimulated neurons. Incorporation of multichannel recording electronics would typically require trans-scleral cables for power supply and data transmission. In this work, we explore a wireless, optoelectronic, miniature, modular, and distributed electro-neural interface for recording, which we call Sensory Particles with Optical Telemetry (SPOT). It can be used in an advanced, bi-directional retinal prosthesis and other sensory applications. Emphasis is placed on the novel telemetry stage. SPOTs are powered by near-infrared light and transmit information by light. As a proof of concept, we designed and built a low-power, small-footprint linear transconductance circuit utilizing chopper stabilization in 130nm CMOS. Our design achieved 57 mS transconductance within 3.5 kHz bandwidth, and a near-infrared (NIR) power density of 0.5 mW/mm2, well within the ocular and thermal safety limits. The telemetry circuit consumes 0.015 mm2area, and each SPOT can be powered by a single photovoltaic (PV) supply of area 0.0056 mm2. Electrical spikes transmitted by an 850nm LED were detected with 15 dB SNR, at the output of the optical link.

Modeling linear periodically time-varying (LPTV) circuits is challenging due to the presence of frequency translation. Many approaches have been proposed that simplify the analysis and provide intuition into the operation of these circuits. It is critical to select the proper model when designing LPTV systems: too complex, and intuition is lost; too simple, and numerical accuracy degrades. This work shows how a conversion matrix-based model can be used for mixer-first receivers with complex feedback in the presence of finite switch transitions. This model accurately predicts S11below -10 dB for all tested transition times, in contrast with prior models, which are shown to be invalid with transitions beyond 2% of the clock period. As a design tool, this approach models gain, harmonic rejection ratio, and noise figure within 0.1 dB of simulation with switch transitions even at 5% of the clock period.

This paper describes an architecture for the massively parallel digitization of neural action potentials. The scheme achieves simultaneous data compression and channel multiplexing through wired-OR interactions within an array of single-slope A/D converters. The achieved compression is lossy but effective at retaining the critical samples belonging to action potential spikes. Simulation results using ex-vivo experimental data from a 512-channel array show compression rates up to ~73x while maintaining ≥90% reconstruction coverage for parasol cells in the primate retina.

Always-on sound classification is a desirable but power-intensive function for a variety of emerging Internet of Everything applications. This work explores the accuracy-complexity tradeoff by using summary statistics for classifying semi-stationary sounds. Compared to contemporary solutions including deep learning, this approach requires one to three orders of magnitude fewer parameters and can therefore be trained over ten times faster. We propose a mixed-signal design using N-path filters for feature extraction to further improve energy efficiency without incurring a large accuracy penalty for a binary classification task (less than 2.5% area reduction under receiver operating characteristic curve).

This paper presents a novel pipeline configuration for wireless applications. Redundancy and multi sampling of the input techniques are used for overcoming the main limitations of pipeline ADCs. A special pre-amplifier with built-in thresholds generation is also discussed. The circuit, designed and simulated in a 65-nm CMOS technology, achieves 2.66 GS/s and 8-bit resolution. The supply voltage is 1V and the simulated power consumption is 22.06 mW, which leads to a FoM of 32.4 fJ/conversion-step.

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.