In this paper, we present a fully integrated ring-oscillator (RO)-based temperature sensor for quantum computing applications. As the quantum states exhibit an exponential sensitivity to the on-die cryogenic temperature change, any such temperature variation due to, for example, local heating islands arising from the poor thermal conductivity of silicon should be monitored. For this purpose, we exploit a compact RO sensor placed in the vicinity of qubits. The proposed approach employs four differently sized oscillators and two VBGs to generate, in total, eight different temperature-dependent oscillating frequency signals. Then, by performing their polynomial fitting, a linear temperature-frequency compensating model for the proposed sensor is derived. Fabricated in 22 nm FD-SOI technology, the proposed sensor occupies 0.0016 mm2, consumes 128 μW and achieves maximum inaccuracy of ± 2.1 K in a wide temperature range from 3 to 270 K.

In this paper, we present an inverter-based ring oscillator (RO) operating at cryogenic temperatures for quantum computing applications. It employs a low-dropout regulator (LDO) to provide supply voltage for a programmable switched-capacitor system which isolates the supply line of the integrated RO circuit from any noise or perturbations of the external power supply. In anticipation of embedding the RO into a phase-locked loop (PLL), we study the variation of flicker phase noise from cryo to room temperature by indirectly measuring the phase noise (PN) in the 30dB/dec region. The proposed system occupies 0.012mm2and shows 3.5dB integrated PN improvement thanks to the proposed voltage supply noise reduction technique at room temperature (RT) and the FOM is estimated as 121.7dB at cryogenic temperature (CT).

Gain-cell (GC) based eDRAM has been a promising memory topology due to the lower area footprint and energy consumption than its SRAM counterpart. However, the eDRAM suffers from a short retention time in finer technology nodes. Enhancing the retention time requires both pMOS and nMOS devices, but this inadvertently increases the cell size due to the minimum spacing between them. Further, the retention time is dominated by either logic ‘1’ or ‘0’, lowering the overall retention time. In our work, we propose an nMOS-only GC-based 4T GC-eDRAM memory topology that occupies an area comparable to the 3T GC-eDRAM and enhances the retention time by balancing logic ‘0’ and ‘1’ via controlling the leakage path. Designed in GlobalFoundries 22-nm FD-SOI, the post-layout simulation of a dual port 128×128 (4kb) eDRAM memory array shows 610 μW and 490 μW of write and read power consumption at 250 MHz, respectively, while maintaining the retention time of 25 μs. The 4T bit-cell with the logic design rule only occupies 0.12 μm2, which is 1.5× lower than the two-port 8T SRAM cells in the PDK, while 1.1× larger than the single-port 6T SRAM.

In this paper, we present the characterisation of ring oscillator (RO) test circuits fabricated in GlobalFoundries’ (GF) 22nm fully depleted silicon-on-insulator (FD-SOI) process and operating from 200 K down to 4 K. We investigate ROs using NAND, NOR, and inverter standard cell libraries, including low, regular, and high threshold-voltage versions. Alongside temperature variations, we also consider a change in the power supply of ±5% from a nominal 0.8 V. The ROs demonstrate the combined effect of increased mobility, increased threshold voltage, and leakage current processes at cryogenic temperatures on their operation. By averaging over 81 fabricated ROs using three different delay gates and 2 different flavours, we report a statistical characterisation of their properties in the FD-SOI technology over temperature and supply voltage.

We describe a quantum computing hardware paradigm that exploits the current scaling achievements of mainstream CMOS technology. Just like in a small IC chip, where a single nanometer-sized CMOS transistor can be reliably replicated millions of times to build a digital processor, we propose a new structure of a qubit realized as a CMOS-compatible charge-based quantum dot that can be reliably replicated thousands (or perhaps even millions) of times to construct a quantum processor. Combined with an on-chip CMOS controller, it will realize a useful quantum computer (QC) that can operate at 4 K, which is much higher than the temperature of today's QCs of 15 mK.

The aim of this paper is to formalise the term “complexity” in the context of modern microelectronics, propose the definitions of key terms and discuss a case study. Our aim is to show that the term “complex system” is implicitly related to the design of electronic systems.