We present hls4ml , a free and open source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this article, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Most scientific discoveries depend on identifying novel signals hidden in massive, noisy datasets generated by modern experiments. Traditional novelty detection methods are often insufficient in speed, robustness, and adaptability to resource-constrained environments. We discuss a perspective on a hierarchical framework for multi-level novelty detection spanning sensor signals, feature representations, and model outputs. At the signal level, we discuss analog circuits that extract statistical densities and moments in real-time, enabling interpretable and energy-efficient filtering. At the feature level, we introduce Likelihood Regret, an unsupervised measure that detects anomalies by retraining generative models on shared latent representations, with optimizations for embedded deployment. At the output level, we leverage predictive uncertainty, applying both compute-efficient Monte Carlo reuse and Monte Carlo-free techniques like evidential learning and conformal inference. Our framework demonstrates how integrating novelty detection across the sensing-to-inference can accelerate insights in domains such as high-energy physics.

Low latency inference has many applications in edge machine learning. In this paper, we present a run-time configurable convolutional neural network (CNN) inference ASIC design for low-latency edge machine learning. By implementing a 5-stage pipelined CNN inference model in a 3D ASIC technology, we demonstrate that the model distributed on two dies utilizing face-to-face (F2F) 3D integration achieves superior performance. Our experimental results show that the design based on 3D integration achieves 43% better energy-delay product when compared to the traditional 2D technology.

We present a prototype smart pixel concept test chip, designed in CMOS 28 nm bulk process, showing a proof-of-concept readout integrated circuit (ROIC) designed for a future Phase III high luminosity upgrade of the large Hadron collider. The presented design employs a synchronous analog-to-digital converter (ADC) for the frontend design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is, therefore, capable of accurately detecting hits occurring in consecutive bunch crossings without off-time registration of events and pileup insensitivity, making it particularly suitable for the innermost layers of the vertex detector. The ROIC consists of a matrix of$32\times 16$pixels, each$25\times 25\ \mu \mathrm{m}^{2}$in size. Each pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The total power consumption is$\sim 4\ \mu\mathrm{W}$per pixel. The measured noise at the output of all the hit comparators across the ROIC is$< 45\ \mathrm{e}_{\text{RMS}}^{-}$, which allows an in-time threshold setting of ≈ 475 e−.

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a$50\ \mu \mathrm{m}\times 50\ \mu \mathrm{m}$footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with$0.48\ \mathrm{e}_{\text{rms}}^{-}$equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of$9,000\ e^{-}$at the lowest gain setting (or$900\ e^{-}$at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of$40\ \mu W$per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm 2 area and has an input referred noise of 2.7$\mu \text {V}_{\text {rms}}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${\text {e}^{-}}$RMS by averaging 1000 samples with MIDNA both at room temperature and at 180Kelvin.

In this article, a low-power, high-speed arbitration tree for pixel detector readout is presented. The synchronized, binary tree priority encoder establishes a position-dependent priority list at the start of every time frame. Pixels that indicate the presence of data for readout are sequentially granted access to a shared bus for data transfer to the periphery, without the use of an additional global strobe signal. It can be used for either full frame imaging or zero-suppressed readout, in which case it can simultaneously generate the pixel address. To increase the readout frame rate, the pixel array is subdivided into two halves, which allow interleaved latching of data at the output serializer. The design was implemented in a 65-nm LP-CMOS process for the readout of a 64×64 pixel array. Measurement results demonstrate a deadtimeless, full frame imaging rate of ~50 kfps, achieved with a dedicated output for every (32×32) 1024 pixels and for a pixel data packet of 11 bits, with no bit errors detected over 1000 frames. The measured energy per bit is 0.94 pJ.

The nano-injection sensor is a new approach towards high-sensitivity short-wave infrared photon imagers. It resolves the conflict of requiring a large area for high quantum efficiency and small area for high fidelity by using a relatively large micron-scale absorbing volume, and nano-scale sensing elements, which regulates the electron flow and amplifies the signal. The front-end electronics for the Single Photon Imaging nano-injection detector consists of an ROIC with 32 × 32 pixel array with a pixel size of 100μm × 100μm. Each pixel consists of a charge sensitive preamplifier with leakage current compensation circuit, a shaping amplifier, an AC-coupled comparator with a 7bit trimming DAC for offset cancellation, a 10-bit counter for photon counting, and a 10-bit shift register for data readout. The ROIC provides dead-time less, continuous readout with 32 parallel LVDS outputs to achieve full frame readout within 5 μs. Simulation results of the ROIC are presented in this work.