As conventional computers based on von Neumann architecture approach their physical and performance limits, unconventional computing paradigms such as Cellular Neural Networks (CellNNs) have emerged as promising platforms for real-time, massively parallel analog computation. However, conventional analog CellNNs suffer from scalability and power constraints due to large cell hardware overhead. This work investigates the integration of memristor-based crossbar arrays into CellNN architectures to address these limitations by exploiting their analog tunability, high density, and low power operation. A 1-Transistor-1-Memristor (1T1R) crossbar is proposed for implementing the coupling weights defining the CellNN gene. Device nonlinearity, asymmetry and stochastic variability are incorporated using the physics-based JART VCM memristor model, enabling accurate mapping of target weights onto memristor conductances through numerical optimization and differential-pair encoding. Simulations of edge detection tasks confirm high functional accuracy and robustness, while Monte Carlo analysis reveals variability’s impact, underscoring the need for variability-aware design of reliable memristor-CNN hardware.

In this work, we introduce a high speed and area efficient Cellular Nonlinear Network (CNN) cell, featuring two circuit variants that utilize threshold switches. The threshold switch (TS) model employed represents a current-controlled nanoscale negative differential resistance (NDR) device which exhibits an S-shaped DC I-V curve as a fingerprint. The proposed cell can be considered as the dual of the standard isolated CNN cell where the bistable cell characteristics, originating from the N-shaped voltage-controlled resistor, is implemented through the S-shaped current-controlled TSs. Similarly, the dynamics induced by the parallel capacitor accompanying the nonlinear resistor in the standard cell version are implemented through the internal inductive dynamics of the TSs, resulting in area and speed efficiency. The proposed CNN cell employs a DC voltage source, two bias resistors and 2 TSs, and essentially, features a differential-mode operation which helps to endow it with a symmetric DC I-V characteristic, as is the case for the standard CNN cell. The differential-mode approach further introduces design flexibility as the cell DC I-V characteristic can be adjusted by tuning circuit parameters. We demonstrate the functionality of the proposed cell by implementing image processing tasks ranging from edge detection and thresholding to logic AND and OR operations.

Quantum computing is a compelling new technology that is becoming increasingly practical as time progresses. Quantum computers have the potential to solve problems of great complexity and magnitude across many different industries, utilizing appropriate quantum algorithms. Given the evolving stage of quantum computing, characterized by a limited number of operational quantum computers that demand extensive cooling, face decoherence issues, and incur significant fabrication costs, there exists a pronounced need for quantum computer simulators. In this work, a reconfigurable closed-loop CBRAM crossbar system has been developed for the execution and acceleration of quantum algorithm simulation, leveraging analog in-memory computing. The circuit supports a universal set of quantum gates representation, and through its reprogramming capabilities and feedback loop, can compute any quantum algorithm. To demonstrate its functionality, the 3-qubit Grover algorithm is executed on the proposed circuit. Building on the extensive circuit simulation, a comparative analysis of power and speed between the proposed nanoelectronic circuit and conventional hardware has been conducted, demonstrating the high efficiency and performance gains, followed by a scalability analysis. Furthermore, a framework has been developed that supports the design of custom closed-loop memristive crossbars through a graphical user interface (GUI), providing the user with the capability to execute quantum algorithms and examine the programming and computations of the circuit, assisting with the realization of a hardware prototype.

The electrical engineering community, interested to develop bio-inspired circuits, approaching the efficiency of the neural networks, is searching passionately for accurate yet simple electronic neurons, or neuristors for short. In recent years, the advent of volatile memristor devices, typically referred to as threshold switches, which admit a negative differential resistance under suitable polarization, similarly as the sodium and potassium ion channels across neuronal axon membranes, has opened up new exciting opportunities in neuromorphic circuit design, enabling innovative analogue electronic cells, capable to reproduce closely the intricate dynamical behaviors of biological neurons without requiring a disproportionate use of resources. The study, presented in this manuscript, achieves an important milestone in this area of research, demonstrating, through a circuit design approach based upon concepts and techniques from Dynamical System Theory, how to leverage the rich dynamics of a threshold switch, capable to boost a periodic sine-wave current signal of infinitesimal amplitude, while acting as a source of local energy, when poised on a suitable bias point, lying along the negative differential resistance branch of the respective S-shaped DC current-voltage characteristic, to induce, one after the other, the three fundamental bifurcations, governing the evolution of an electrical voltage spike from birth to extinction via the All-to-None effect across a biological axon membrane under a reverse sweep in the net synaptic current, according to the fourth-order Hodgkin-Huxley neuron model, in a second-order three-element circuit of unprecedented simplicity, as the current, generated by a DC source, appearing in parallel to a linear capacitor as well as to the volatile locally-active memristor, is subject to a monotonic increase.

This manuscript sheds light into the fundamental importance of the Principles of Local Activity and Edge of Chaos for the future design of innovative circuits, which, employing biomimetic memristive devices, are ideally suited for the development of energy-efficient artificially-intelligent technical systems. The focus of the work is the design of a Second-Order Reactance-Less Oscillator, across which oscillations may develop if and only if at least one of its two different volatile thermally-activated memristor physical realizations is biased along a negative differential resistance branch of the respective DC locus, which turns it into a source of local energy. Very importantly, the proposed cell is first found to lock in the oscillatory mode out of a local Hopf Supercritical Bifurcation when its design parameters are chosen from the Edge of Chaos region, providing clear evidence for the high degree of excitability it acquires as a result.

Neuromorphic circuits using emerging memory technologies have recently gained popularity since they facilitate dense integration with reduced design complexity. In this work, we introduce a simplified modeling approach for the analysis of threshold switch (TS) based neuron circuits where, under given constraints, we represent the TS device as a nonlinear resistor in series with a parasitic inductor. As a result, we define the current of the TS as its state variable. In order to demonstrate the feasibility of the proposed approach, we analyze the conventional Leaky Integrate and Fire (LIF) neuron circuit along with two of its modified variants. We validate the accuracy of the provided analysis and key predictions through numerical simulation results. As a significant contribution, we demonstrate the effectiveness of the proposed method in modifying the nullclines of the TS based LIF neuron and qualitatively align them with the nullclines of a 2ndorder biologically plausible neuron model.

As demand grows for efficient edge computing systems, innovative architectures are crucial for achieving low-power, high-density data processing in resource-constrained environments. Compressed sensing (CS) and Analog In-Memory Computing (AIMC) offer promising pathways to meet these needs by enabling localized, efficient feature extraction and inference. This paper introduces an energy-efficient on-chip system that integrates CS with AIMC based on Phase-Change Memory (PCM) devices to enable robust feature extraction and inference. The proposed architecture employs CS for dimensionality reduction at the sensor level, generating low-dimensional feature vectors directly fed into a single-layer artificial neural network (ANN) implemented on PCM crossbars. To address inherent hardware non-idealities, we utilize hardware-aware (HWA) training combined with an attention-based regularization mechanism, improving both inference stability and drift resilience over extended periods. Performance evaluation on a face recognition task demonstrates that attention-enhanced HWA training effectively mitigates overfitting and maintains model accuracy under PCM drift conditions, highlighting the system's suitability for edge computing applications requiring low power consumption and long-term reliability.

Realized memristors exhibit a unique phenomenon called the fading memory effect, where the memristor response to an AC signal is determined by its characteristics (waveform, amplitude, frequency, and DC offset) rather than the memristor initial conditions. Recently, a method for programming Hewlett Packard’s TaOxmemristor to a target state was proposed, involving configuring the DC offset of a high-frequency square-wave AC voltage input. This served as a basic application example that exploits fading memory in non-volatile memristors, but didn’t consider non-ideal effects. Here, we assess the method applicability in a HfOx-based VCM resistive switch from Forschungszentrum Julich incorporating a variability-aware physics-based model.

We have successfully fabricated one of the earliest array-scale prototypes of a Memristive Cellular Nonlinear Network (M-CNN) with interconnected cells. In this live demonstration, we will showcase the operation of this 4x4 M-CNN array performing an edge detection task according to our previous work [1]. A user-defined input will be applied to the network, and the computing results will be visualized alongside the simulated operation of a standard CNN for comparison.

As demand grows for efficient, localized processing in edge and in-sensor computing, novel architectural approaches are essential to meet low-power, high-density requirements. Memristor Cellular Nonlinear Networks (M-CNNs) offer a promising path forward, leveraging the unique properties of memristors for adaptable and scalable computation. This paper presents a study of novel M-CNN cell configurations designed to enhance computational versatility and address operational challenges in M-CNN-based systems. By leveraging memristor technology within CNN cells, we propose three distinct configurations: (1) incorporating parallel and series resistive elements for refined control over cell dynamics, (2) introducing a fixed bias voltage to expand computational capabilities, and (3) integrating the Full-Range CNN (FR-CNN) model into M-CNNs for the first time. The proposed topologies are evaluated through dynamic route maps (DRM) and vector field analysis to systematically assess stability and performance across varying design parameters.

In this paper, the design of an isolated Memristor Cellular Nonlinear Network (CNN) cell with discrete electronic elements is presented. The proposed versatile circuit allows for adjustable cell dynamical characteristics, controlled by design parameters, while the discrete element approach enables simple on-board implementation without the need for large-scale integration, which is necessary for testing hardware with individual fabricated memristors. A voltage-mode approach, that makes use of the diversity of operational amplifiers, is preferred here over a current-mode one that necessitates a large number of individual transistors. The dynamical properties of the system are initially investigated through the calculation of equilibrium points and further illustrated applying the concept of State Dynamic Routes (SDRs) for the cell assuming that the memristor dynamics are much slower than the capacitor voltage dynamics. Moreover, the effect of design parameters on the cell dynamics is being investigated, showing how the scaling of the operating voltage, as well as a plethora of CNN variants -i.e., the Chua-Yang and Full Range models-, can be implemented within the same design. Finally, the nonlinear conductance properties of real memristor devices are incorporated into the study, demonstrating interesting bifurcation phenomena between the cell monostability and bistability for specific parameter values.

Biological synapses behave as dynamically-rich nonlinear elements, participating in complicated computing tasks through their adaptation due to external stimuli. Such adaptivity constitutes an intrinsic property of non-volatile memristor devices, which are also able to maintain their internal state, under zero input, enabling novel bio-inspired learning operations. In this work, a synaptic element based on a memristive bridge, containing two resistors and two memristors, is studied, aiming to investigate complex memristor-based topologies that may result in rich synaptic dynamics. The proposed memristive bridge allows the realization of both positive and negative synaptic weights, while an asymmetric tuning of a weight, stemming from memristor's features and bridge topology, is demonstrated. In particular, by properly selecting the memristor's position and polarity within the bridge, different tuning behaviors have been observed, showcasing versatile learning properties of the topology. Along with the synaptic weight tuning, the read overall process of the synaptic weight, necessary for inference operations, is also investigated. We explore the dynamics of the bridge via numerical simulations.

The so far dominant Von Neumann architecture is being challenged by the energy demanding communication bottle-neck between processing and memory units. To address this issue, in-memory computing is employed for their co-location, with memristive crossbar arrays playing an important role towards this goal. Motivated by the above, this work introduces a timing-based programming of a memristor crossbar array for sequence generation in Stochastic Computing (SC). Its operation principle is based on the stochastic nature of the memristor devices forming the crossbar array, where their programming is regulated by the switching probability that follows the Poisson distribution, controlled by pulse amplitude and duration. The timing-based programming of the proposed crossbar array increases the discretization levels of the output probability values, thereby offering more accurate control when compared to programming schemes that consider only the pulse amplitude. The memristor's stochasticity along with the crossbar's inherent parallelism opens the in-memory design space allowing SC elements to be used as sequences are generated efficiently. Simulation results on different programming pulse-width precisions highlight the proposed crossbar's effectiveness in sequence generation, supported by mean absolute error (MAE) results in a standard SC arithmetic operation. Process variations stemming from the crossbar array affecting the sequence generation in SC are investigated.

The memristor crossbar architecture is a new technology that combines memory and computing on the same chip, finding numerous applications in modern bio-inspired computing systems. Recently, memristor-coupled Chua Circuit Networks (MCCNs) have been developed for the experimental confirmation of collective nonlinear phenomena, such as chimera states, that are also observed in the brain. For highly dense topologies, however, memristor crossbars can be prone to certain vulnerabilities. In this paper, we investigate the impact of sneak-path currents (SPCs) on the collective behaviors of chaotic oscillator networks, uncovering the network's tolerance to various realistic memristor crossbar designs. Despite the fact that these states alter the synchronization regime map, our findings suggest that SPCs have no detrimental impact on the formation and stability of single or multiple chimera states. This coupling issue along with other possible challenges are thoroughly discussed with a focus on nonlinear dynamics, highlighting the reliability of memristor crossbars as a coupling mechanism for studying chimera states.

There is a continuous urge for higher efficiency in conventional computing systems, driven by an ever-growing demand for these systems’ complexity to be able to match the one of convoluted and challenging problems. However, this type of problems has formulated the benchmarks for unconventional computing systems to validate their emerging applicability and prove their effectiveness. Towards this path, Cellular Automata (CAs) have been established as a promising mathematical tool for simulating physical processes and demonstrated a favourable methodology for effectively implementing computations in hardware by taking advantage of their inherent parallelism. Representing CAs with oscillating memristive networks could further enhance the performance of these systems, by incorporating the rich dynamics evident in memristors and their strong memory and computing features. In this work, a wave generator circuit has been designed with low-voltage fabricated CBRAM devices, that is able to act as a Wave Cellular Automaton (WCA). These wave generation units are located on a grid with adjusting multi-directional interconnections between neighbors. In addition to that, the ability to reconFigure the amount of such units that influence each other, facilitates the propagation of voltage signals through the grid following wave propagation features. An example of this computational domain is presented with the realization of complex logic gates on the grid of WCAs.

The threshold switching effect is critical in memristor devices for a range of applications, from crossbar design reliability to simulating neuromorphic features using artificial neural networks. The rich inherit dynamics of a metallic conductive filament (CF) formation are thought to be linked to this characteristic. Simulating these dynamics is necessary to develop an accurate memristor model. In this work we present a compact memristor model that utilizes the drift, diffusion and thermo-diffusion effects. These three effects are taken into consideration to derive the switching behavior of a memristor. The resistance of a memristor is calculated based on the evolution of a truncated cone shaped filament. The objective of this model is to achieve a realistic integration of switching mechanisms of the memristor device, while minimizing the overhead on computing resources and being compatible with circuit design tools. The model incorporates the effect of thermo-diffusion on the switching pattern, providing a different perception of the ionic transport processes, which enable the unipolar switching. SPICE simulation results provide an exact match with experimental results of Metal-Insulator-Metal (MIM) memristive devices of Ag/Si2/SiO2.07/Pt nanoparticles (NPs) configuration.

The beneficial role of noise in the performance of Hf-based memristors has been experimentally studied. The addition of an external gaussian noise to the bias circuitry positively impacts the memristors characteristics by increasing the OFF/ON resistances ratio. The known stochastic resonance effect has been observed, when changing the standard deviation of the noise. The influence of the additive noise on the memristor current-voltage characteristic and on the set and reset related parameters are also presented.

There is a growing interest in quantum computers and quantum algorithm development. It has been proved that ideal quantum computers, with zero error rates and large decoherence times, can solve problems that are intractable for today’s classical computers. Quantum computers use two resources, superposition and entanglement, that have no classical analog. Since quantum computer platforms that are currently available comprise only a few dozen of qubits, the use of quantum simulators is essential in developing and testing new quantum algorithms. We present a novel quantum simulator based on memristor crossbar circuits and use them to simulate well-known quantum algorithms, namely the Deutsch and Grover quantum algorithms. In quantum computing the dominant algebraic operations are matrix-vector multiplications. The execution time grows exponentially with the simulated number of qubits, causing an exponential slowdown in quantum algorithm execution using classical computers. In this work, we show that the inherent characteristics of memristor arrays can be used to overcome this problem and that memristor arrays can be used not only as independent quantum simulators but also as a part of a quantum computer stack where classical computers accelerators are connected. Our memristive crossbar circuits are re-configurable and can be programmed to simulate any quantum algorithm.

Over the last years there has been significant progress in the development of quantum computers. It has been demonstrated that they can accelerate the solution of various problems exponentially compared to today's classical computers, harnessing the properties of superposition and entanglement, two resources that have no classical analog. Since quantum computer platforms that are currently available comprise only a few tenths of qubits, as well as the access to a fabricated quantum computer is time limited for the majority of researchers, the use of quantum simulators is essential in developing and testing new quantum algorithms. Taking inspiration from previous work on developing a novel quantum simulator based on memristor crossbar circuits, in this work, a framework that automates the circuit design of emulated quantum gates is presented. The proposed design framework deals with the generation and programming of memristor crossbar configuration that incorporates the desirable quantum circuit, leading to a technology agnostic design tool. To such a degree, various quantum gates can be efficiently emulated on memristor crossbar configurations for various types of memristive devices, aiming to assist and accelerate the fabrication process of a memristor based quantum simulator.

The time series of the brain are usually characterized by the co-existence of synchronized and desynchronized behaviors. This kind of behavior is related to normal and disorderly functions of the brain. One of the suggested mechanisms to understand thoroughly this behavior are chimera states, which are characterized by the coincidence of coherent and incoherent dynamics that can be exploited through networks of symmetrically coupled identical oscillators. In this work, ring-based networks of Chua's circuits, the simplest electronic oscillators that perform chaotic and well-known bifurcation phenomena, have been extensively studied in memristive crossbars (Xbar), revealing various collective spatio-temporal behaviors, such as chimera states. With respect to different Xbar connectivities and via SPICE-level circuit simulations, the proposed Xbar system proves its efficacy to reproduce spatio-temporal patterns spanning from complete synchronization and chimera states up to fully chaotic states.

Research progress in edge computing hardware, capable of demanding in-the-field processing tasks with simultaneous memory and low power properties, is leading the way towards a revolution in IoT hardware technology. Resistive random access memories (RRAM) are promising candidates for replacing current non-volatile memories and realize storage class memories, but also due to their memristive nature they are the perfect candidates for in-memory computing architectures. In this context, a CMOS compatible silicon nitride (SiN) device with memristive properties is presented accompanied by a data-fitted model extracted through analysis of measured resistance switching dynamics. Additionally, a new phototransistor-based image sensor architecture with integrated SiN memristor (1P1R) was presented. The in-memory computing capabilities of the 1P1R device were evaluated through SPICE-level circuit simulation with the previous presented device model. Finally, the fabrication aspects of the sensor are discussed.

Memristor networks are capable of low-power and massive parallel processing and information storage. Moreover, they have presented the ability to apply for a vast number of intelligent data analysis applications targeting mobile edge devices and low power computing. Beyond the memory and conventional computing architectures, memristors are widely studied in circuits aiming for increased intelligence that are suitable to tackle complex problems in a power and area efficient manner, offering viable solutions oftenly arriving also from the biological principles of living organisms. In this paper, a memristive circuit exploiting the dynamics of oscillating networks is utilized for the resolution of very popular and NP-complete logic puzzles, like the well-known “Sudoku”. More specifically, the proposed circuit design methodology allows for appropriate usage of interconnections' advantages in a oscillation network and of memristor's switching dynamics resulting to logic-solvable puzzle-instances. The reduced complexity of the proposed circuit and its increased scalability constitute its main advantage against previous approaches and the broadly presented SPICE based simulations provide a clear proof of concept of the aforementioned appealing characteristics.

Since CMOS technology approaches its physical limits, the spotlight of computing technologies and architectures shifts to unconventional computing approaches. In this area, novel computing systems, inspired by natural and mostly nonelectronic approaches, provide also new ways of performing a wide range of computations, from simple logic gates to solving computationally hard problems. Reaction-diffusion processes constitute an information processing method, occurs in nature and are capable of massive parallel and low-power computing, such as chemical computing through Belousov-Zhabotinsky reaction. In this paper, inspired by these chemical processes and based on the wave-propagation information processing taking place in the reaction-diffusion media, the novel characteristics of the nanoelectronic element memristor are utilized to design innovative circuits of electronic excitable medium to perform both classical (Boolean) calculations and to model neuromorphic computations in the same Memristor-RLC (M-RLC) reconfigurable network.

Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other hand, is a fundamentally nonlinear circuit element, thus susceptible to benefit from SR, which recently came in the spotlight of the emerging technologies potential candidates. However, at this time, the variability exhibited by manufactured memristor devices within the same array constitutes the main hurdle in the road towards the commercialisation of memristor-based memories and/or computing units. Thus, in this paper, memristor SR effects are explored, assuming various memristor models, and SR-based memristance range enhancement, tolerant to device-to-device variability, is demonstrated. Our experiments reveal that SR can induce significant RMAX/RMINratio increase under up to 60% variability, getting as high as 3.4× for 29 dBm noise power.

Cellular Automata (CA) is a nature-inspired and widespread computational model which is based on the collective and emergent parallel computing capability of units (cells) locally interconnected in an abstract brain-like structure. Each such unit, referred as CA cell, performs simplistic computations/processes. However, a network of such identical cells can exhibit nonlinear behavior and be used to model highly complex physical phenomena and processes and to solve problems that are highly complicated for conventional computers. Brain activity has always been considered one of the most complex physical processes and its modeling is of utter importance. This work combines the CA parallel computing capability with the nonlinear dynamics of the memristor, aiming to model brain activity during the epileptic seizures caused by the spreading of pathological dynamics from focal to healthy brain regions. A CA-based confrontation extended to include long-range interactions, combined with the recent notion of memristive electronics, is thus proposed as a modern and promising parallel approach to modeling of such complex physical phenomena. Simulation results show the efficiency of the proposed design and the appropriate reproduction of the spreading of an epileptic seizure.

Unconventional computing has been studied intensively, even after the appearance of CMOS technology. Currently, it has returned to the spotlight because CMOS is about to reach its physical limits, given that the constant demand for more computational power requires for novel unconventional computing solutions. In this area, the oscillatory internal motion mechanism of slime mould, namelyPhysarum Polycephalum, could serve as an alternative concept for the design and development of electronic circuits that exploit the memristive dynamics and simple LC contours to deliver solutions for computationally hard to be solved problems. In this direction, this work presents how bio-inspired memristive LC oscillators with a coupling capacitor can be synchronized to perform the functionalities of a biological neuron, also able to execute more complex computations, aiming to model biological neural systems much more advanced than the neuron-less slime mould biological organism. This work proposes a connection between the function mechanism of a simple biological organism and that of complex biological systems, made in a plausible and sufficient manner, towards unconventional computation with memristors.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Within an ever-increasing variety of applications for memristors, adaptive electronic circuits have attracted considerable attention lately. This paper extends previously published work on memristive filter design to include the potential of composite memristive devices as damping elements in LC-based sensing circuits. The collective response of several LC contours with different memristive damping is considered. A thorough study of the circuit properties is performed in an attempt to exploit the high sensitivity of the circuit, other than address it as a typical drawback. The simulated circuits could find application in bio-inspired information processing, whereas could lead to better behavioral models for biological organisms.