This paper presents the design of a fully flexible temperature sensor for wearable applications. The sensor is implemented using the newly available flexible integrated electronic circuit (Flex-IC) technology from Pragmatic Semiconductor [1]. To address the design challenges due to the limited set of thin film components available in this non-CMOS technology, a counter-based time-to-digital conversion (TDC) technique has been developed, where the pulses provided by a temperature-dependent ring oscillator are gated and counted by a temperature-independent delay cell. The operation of the delay cell relies on the temperature coefficient cancellation of resistive components by a cross-coupled pair. A tunable calibration mechanism is also incorporated in the design to handle the process corners in a temperature range of 32 °C - 42 °C suitable for biological sensing. The presented sensor design exhibits a low time-jitter induced measurement error, with a 0.81 % probability of toggling the least significant bit (LSB) per sample, maintaining 0.1 °C precision and a zero-error range of 6.8 °C, while dissipating a power of 2.5 mW with an acquisition time of 3 ms. The chip layout measures 3.0 mm×3.0 mm with a die thickness of 30 μm. Compared to existing rigid and hybrid systems, the Flex-IC technology opens up opportunities for advancing conformal electronics, particularly for applications requiring continuous monitoring on dynamic body surfaces.

This paper proposes a new curriculum for under-graduate students that teaches chip-level design and assembly for developing a complete, tapeout-ready System-on-Chip (SoC) that includes synthesized digital components, analog/mixed-signal blocks, and IP such as memories and I/O drivers. The course will guide students through the process of synthesizing RTL into layout blocks, floor planning, chip-level routing of components, simulation, verification, and tapeout using a 45 nm public-domain PDK. By the end of the class, students will be capable of designing a complete, verified, and tapeout-ready SoC containing complex digital microcontroller circuitry and analog/mixed-signal front-ends. The course will take students through the steps to design and assemble a chip based on an existing SoC designed at the authors’ university. This will lead to the development of a workforce capable of designing mixed-signal SoC solutions for broader industrial and academic needs.

This work presents a single-chip electronics interface for low power, high count rate gamma ray spectroscopy using a novel current nulling scheme that reduces power consumption to 8.8 mW at a count rate of 30 kcps. The current nulling circuit monitors and subtracts the time-varying PMT anode bias network current that would normally lead to a significant integration error at high count rates. This allows the use of low power, event-driven circuit topologies downstream at higher count rates than would otherwise be supported. With this method, the detection resolution degradation improves from 0.85%70/kcps to 0.02%/kcps and the spectrum shift is reduced from −22bins/kcps to 0.32 bins/kcps.

Electronic skin (e-skin) interface building blocks are presented that are suitable for integration with array-based tactile sensors for prosthetic applications. The first is a low power, low noise capacitive transimpedance amplifier (CTIA) compatible with charge-based polyvinylidene fluoride (PVDF) sensors. The second is a high efficiency RISC-V microcontroller unit (MCU) with a custom, on-chip neural processing unit (NPU) to accelerate gesture recognition tasks. Two test chips have been fabricated using a 65 nm CMOS technology: one for the prototype analog front-end (AFE) including the CTIA, and the other for the MCU and NPU. The AFE consumes 112.5 nW per channel, and the MCU consumes 2.83 mW while running the NPU at 112 MHz.

A standalone radiation detection and identification system is designed and tested which quantizes gamma ray energies with a scintillator, photomultiplier tube, and a custom multichannel analyzer chip to construct a gamma ray energy histogram. The histogram is used as the input to a fast, low memory, versatile neural network that runs in software on a microcontroller and identifies in real time which radioisotopes are present in the radiation source. The neural network accurately identifies the radioisotopes for which it has been trained, running in under 91.4 ms, consuming less than 6.2 kB of memory, and expending 274 μJ of energy each time it is executed.

A low-power, single-chip electronic skin interface is presented. Its small size and reduced battery requirements are ideal for advanced prosthetic limbs that utilize electronic skin to provide their user tactile feedback. The architecture consists of multiple charge-sensitive analog front ends (AFEs) interfaced to a central, 16-bit microcontroller core which is capable of processing the sensory information in real-time. Event-driven operation allows the chip to monitor all input channels while idle and consuming minimal energy. A test chip has been fabricated in a 0.13 μm CMOS technology and implements 13 AFE channels. Its functionality is demonstrated by interfacing the chip to a prototype electronic skin based on polyvinylidene fluoride (PVDF) piezoelectric sensors. Signals from the sensors are captured by the presented chip and processed to calculate the corresponding charge. This is accomplished by programming the microcontroller with a custom software algorithm implemented in C, granting the system the flexibility to interface to different types of sensors. The single-chip electronic skin system consumes 7.0 μW per channel and 76.5 μW in the example application, making it suitable for use with battery-powered prosthetics.

This paper presents the design and test results of a low-power radiation detection system. When paired with a scintillation-based detector, the design forms a compact, portable unit suitable for use in long-duration radiation monitoring applications. The system consists of two distinct modules. The first is a low-power detector power supply (DPS) used to generate multiple high voltages necessary to bias a photomultiplier tube (PMT), which is controlled and regulated by a 0.35 μm controller chip. The second is a 0.13 μm low-power multichannel analyzer (MCA) chip with an integrated microcontroller and event-driven charge-sensitive front-ends with 10-bit ADCs used to acquire and analyze the energy spectrum of the radiation. The MCA interfaces with the DPS through a digital interface, allowing it to tune the PMT voltage to compensate for temperature and time variations in the detector. Both modules were fabricated and tested to verify low-power functionality, consuming 2.4 mW when sensing radiation events at 1000 counts/sec (cps).

This work presents a smart camera application of real-time trajectory calculation, utilizing a neighborhood-level parallel processing vision chip to track objects and predict their path of motion. The vision chip contains arrays of pixel elements embedded into neighborhood processors, which are tiled to create a 64×80 resolution vision chip. The high frame rate and processing speed of the vision chip allows for calculation of the object's trajectory before leaving the frame. Algorithm design for the tracking algorithm is discussed and hardware test results for linear and non-linear path predictions are presented. Further considerations in optimizing the algorithm for higher precision and robust trajectory forecasting are discussed.

This paper presents the design and test results of a low-power 10-bit multichannel analyzer (MCA) chip for radiation detection. A low-power and event driven charge sensitive front-end and analog-to-digital converter (ADC) are implemented together with a microcontroller on a single chip. This level of integration leads to a compact MCA that can process and build pulse height spectra when interfaced with a range of scintillator detectors, with the ability to digitally process the spectra using software running as embedded code. The design was fabricated in a 0.13 μm CMOS technology and tested to validate the approaches taken. The measured power consumption of the MCA is below 85 μW while detecting multiple radioisotopes.

This live demonstration features a vision chip based on a neighborhood level parallel processing paradigm. Processors are physically embedded within groups of pixels, complete with memory and algorithmic capabilities controlled by a custom instruction set. This results in a scalable resolution, parallel processing vision chip with flexible programmability that can perform a wide variety of image and video processing tasks. A prototype vision chip has been fabricated in a 0.13μm CMOS technology consisting of an 8×10 array of processors with a 64×80 resolution. The setup demonstrates how the vision chip can execute various parallel processing programs and manipulate image acquisition parameters to match the requirements of a scene in real-time.

This paper presents a novel vision chip architecture based on pixel-neighborhood level parallel processing. The architecture consists of neighborhoods of 8×8 digital pixel sensors, where each group of 8×8 sensors is physically embedded within its own neighborhood processing core on the same focal plane. To that end, a low complexity neighborhood processor architecture along with a general-purpose, 8-bit instruction set has been designed and implemented. This allows program execution to be carried out in parallel on a two-dimensional array of pixel-neighborhood processing cores, allowing for direct scalability in terms of resolution. A prototype vision chip housing an array of 8×10 neighborhoods with a 64×80 resolution has been designed and fabricated in a 0.13 μm fabrication process. The single-chip vision system can be programmed to perform a variety of image and video processing tasks. A number of image processing tasks are presented to demonstrate the functionality of pixel-neighborhood level parallelism.