EDBT 2026 Demo / reviewers in the wild / expert
Qiubo Chen
dblp:166/3228
· DBLP profile ↗
6ranked-venue papers
3as first author
2since 2021 · last 2024
0000-0002-0308-8111ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 4 · 2 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 first-authorComputer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Embedded and real-time systems · 25% Hardware reliability and fault tolerance · 25% Integrated circuit design · 22% | |
| Computer networks
1 paper |
Network management and operations · 50% Internet architecture and protocols · 50% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Internet architecture and protocols › time-sensitive networking
deterministic transmission |
0.4 | 1 | 2019 | An Enhanced Reconfiguration for Deterministic Transmission in Time-Triggered Networks · IEEE/ACM Trans. Netw. 2019 |
Network management and operations › network configuration
reconfiguration |
0.4 | 1 | 2019 | An Enhanced Reconfiguration for Deterministic Transmission in Time-Triggered Networks · IEEE/ACM Trans. Netw. 2019 |
Hardware reliability and fault tolerance
reconfiguration |
0.4 | 1 | 2019 | An Enhanced Reconfiguration for Deterministic Transmission in Time-Triggered Networks · IEEE/ACM Trans. Netw. 2019 |
Embedded and real-time systems › real-time communication
time-triggered networks |
0.4 | 1 | 2019 | An Enhanced Reconfiguration for Deterministic Transmission in Time-Triggered Networks · IEEE/ACM Trans. Netw. 2019 |
Integrated circuit design › digital circuit design
VLSI architecture |
0.3 | 1 | 2018 | Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing · IEEE Trans. Multim. 2018 |
Energy-efficient computing › power management
dynamic voltage and frequency scaling |
0.1 | 1 | 2018 | Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display Processing · IEEE Trans. Multim. 2018 |
Methods — techniques the papers use, named apart from their topics
update theory · 0.8dependence graphs · 0.8semi-fixed length coding · 0.3prediction-and-compression · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | SG-JND: Semantic-Guided Just Noticeable Distortion Predictor for Image CompressionabstractJust noticeable distortion (JND), representing the threshold of distortion in an image that is minimally perceptible to the human visual system (HVS), is crucial for image compression algorithms to achieve a trade-off between transmission bit rate and image quality. However, traditional JND prediction methods only rely on pixel-level or sub-band level features, lacking the ability to capture the impact of image content on JND. To bridge this gap, we propose a Semantic-Guided JND (SG-JND) network to leverage semantic information for JND prediction. In particular, SG-JND consists of three essential modules: the image preprocessing module extracts semantic-level patches from images, the feature extraction module extracts multi-layer features by utilizing the cross-scale attention layers, and the JND prediction module regresses the extracted features into the final JND value. Experimental results show that SG-JND achieves the state-of-the-art performance on two publicly available JND datasets, which demonstrates the effectiveness of SG-JND and highlight the significance of incorporating semantic information in JND assessment. Linhan Cao, Wei Sun 0029, Xiongkuo Min, Jun Jia, Zijian Chen 0001, Yucheng Zhu, Lizhou Liu, Qiubo Chen, Guangtao Zhai |
ICIP | 9 |
| 2024 | Content-Adaptive Rate-Quality Curve Prediction Model in Media Processing SystemabstractIn streaming media services, video transcoding is a common practice to alleviate bandwidth demands. Unfortunately, traditional methods employing a uniform rate factor (RF) across all videos often result in significant inefficiencies. Content-adaptive encoding (CAE) techniques address this by dynamically adjusting encoding parameters based on video content characteristics. However, existing CAE methods are often tightly coupled with specific encoding strategies, leading to inflexibility. In this paper, we propose a model that predicts both RF-quality and RF-bitrate curves, which can be utilized to derive a comprehensive bitrate-quality curve. This approach facilitates flexible adjustments to the encoding strategy without necessitating model retraining. The model leverages codec features, content features, and anchor features to predict the bitrate-quality curve accurately. Additionally, we introduce an anchor suspension method to enhance prediction accuracy. Experiments confirm that the actual quality metric (VMAF) of the compressed video stays within ±1 of the target, achieving an accuracy of 99.14%. By incorporating our quality improvement strategy with the rate-quality curve prediction model, we conducted online A/B tests, obtaining both +0.107% improvements in video views and video completions and +0.064% app duration time. Our model has been deployed on the Xiaohongshu App. Shibo Yin, Zhiyu Zhang 0010, Peirong Ning, Qiubo Chen, Guo Lu, Li Song 0001 |
VCIP | 4 |
| 2019 | An Enhanced Reconfiguration for Deterministic Transmission in Time-Triggered NetworksabstractThe emerging momentum of digital transformation of industry, i.e. Industry 4.0, poses strong demands for integrating industrial control networks, and Ethernet to enable the real-time Internet of Things (RT-IoT). Time-triggered (TT) networks provide a cost-efficient integrated solution while RT-IoT arouses the reconfiguration challenges: the network has to be flexible enough to adapt to changes and yet provides deterministic transmission persistently during network reconfiguration. Software defined network benefits the flexible industrial control by configuring the rules handling frames. However, previous reconfiguration mechanisms are mostly oriented to the context of data centers and wide area networks and thus do not consider the deterministic transmission in TT networks. This paper focuses on the reconfiguration (i.e., updates) for the deterministic transmission. To minimize the overhead during updates, namely the minimum number of loss frames and the minimum duration time of updates, we first establish an update theory based on the dependence relationship derived by the conflicts during updates. In addition then the reconfiguration problem is modeled with the dependence graph built by the relationship. On such a basis, we present a reconfiguration mechanism and its implementation to solve the problem. Finally, we evaluate the proposed reconfiguration mechanism in two real industrial network topologies. The experimental results demonstrate that compared with previous methods, our mechanism significantly reduces the number of loss frames and achieves zero loss in almost all cases. Zonghui Li, Hai Wan, Zaiyu Pang, Qiubo Chen, Yangdong Deng, Xibin Zhao, Yue Gao 0002, Ming Gu 0001 |
IEEE/ACM Trans. Netw. | 4 |
| 2018 | Worst Case Driven Display Frame Compression for Energy-Efficient Ultra-HD Display ProcessingabstractDisplay frame compression is an effective technique to address the challenge of external memory access in ultrahigh definition video display system. Nevertheless, previously proposed display frame compression designs are inadequate in terms of either energy efficiency or throughput. This paper aims to exploit the algorithm and very large scale integration (VLSI) architecture of a worst case driven display frame compression. By using a prediction-and-compression framework and a semi-fixed length coding scheme, the proposed design can achieve the much better balance between compression efficiency and throughput, and substantially reduce the bandwidth requirement and energy consumption of external memory system in the meanwhile. Extensive experiments demonstrate that the proposed display frame compression achieves 5.7-dB peak signal-to-noise ratio improvement, 3.1% compression ratio reduction, 3 × throughput, and 66.4% hardware cost saving, compared with the best previous work. In addition, the proposed VLSI design can support the throughput of 4 K × 2 K@60 Hz and reduce at least 17.6% energy consumption of external memory system by exploiting dynamic voltage and frequency scaling, compared with conventional display frame compression works. Qiubo Chen, Hongbin Sun 0001, Nanning Zheng 0001 |
IEEE Trans. Multim. | 1 |
| 2016 | Algorithm and VLSI Architecture of Edge-Directed Image Upscaling for 4k Display SystemabstractHigh-quality and cost-efficient image upscaling design is very important for many real-time video processing applications, especially when the display panel resolution reaches ultrahigh definition. Compared with New Edge-Directed Interpolation (NEDI) based implicit edge directional upscaling, explicit methods require less computational resource and more easily reach real-time performance, especially when the required image definition and upscaling ratio are very high. Nevertheless, the investigation of applications of explicit methods in video processing systems remains largely missing arguably because it is commonly believed that explicit edge-directed interpolation tends to introduce unexpected artifacts because of inaccurate detection and hence its image quality is relatively poor. This paper proposes an explicit edge-directed adaptive interpolation method that leverages more sophisticated edge detection and orientation estimation algorithms to avoid misinterpolation, thereby providing similar or even better image quality than those with implicit methods. Targeting the real-time 4K video display system, the proposed edge-directed image upscaling algorithm is further implemented with an efficient very-large-scale integration (VLSI) architecture. The experimental results demonstrate that the proposed interpolation algorithm outperforms previous explicit and implicit edge-directed methods in both objective and subjective tests. The presented VLSI implementation further demonstrates that the maximum output video sequence of the proposed interpolation method can reach 4k × 2k@60 Hz with a reasonable hardware cost. Qiubo Chen, Hongbin Sun 0001, Xuchong Zhang, Huibin Tao, Jie Yang 0001, Jizhong Zhao, Nanning Zheng 0001 |
IEEE Trans. Circuits Syst. Video Technol. | 1 |
| 2015 | Exploiting bit-depth scaling for quality-scalable energy efficient display processingabstractThe energy efficiency of video display processing is critical for its integration into mobile SoC. This paper proposes a bit-depth scaling scheme to enable dynamic voltage and frequency scaling for external memory system and hence provides a quality-scalable energy efficient display processing solution. Experimental results have demonstrated that the proposed scheme is able to steadily reduce the energy consumption of overall external memory system by up to 23.8%, with graceful image quality degradation and very low cost overhead. Qiubo Chen, Hengyu Zhao, Hongbin Sun 0001, Nanning Zheng 0001 |
ISCAS | 1 |