In this paper, a Low-Temperature Polycrystalline Oxide (LTPO) Thin Film Transistors (TFTs) based power management integrated circuits (PMICs), consisting of both charge pump and low dropout regulator (LDO), are presented for the first time. A charge pump circuit is proposed to convert the supply voltage into both negative and doubled positive voltages with a minimum area overhead, which benefits from a switch-reused hybrid architecture and integration of both P and N type TFTs. A high performance LDO with a fixed-factor feedback network is proposed to reduce the output offset caused by the intrinsic process variation of flexible TFTs. The charge pump has an 8 V input, with outputs of +15.8 V and -7.8 V. With a load current range of 20 µA to 300 µA, the voltage drop across the charge pump remains below 1.2 V, with efficiency consistently exceeding 90% and peaking at 96.5%. The proposed LDO has a 4.53 V output, achieving an ultra-low quiescent current of 311 nA and delivering a load current of 11.6 mA.

Design technology co-optimization (DTCO) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTCO flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners and technology parameters. Validation with 512 unseen technology corners and over one million test data points shows accurate predictions of delay, power, and input pin capacitance for 33 types of cells, with a mean absolute percentage error (MAPE) ≤ 0.95% and a speedup of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error ≤ 3.0 ps for WNS, percentage errors ≤ 0.60% for leakage power, and ≤ 0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.

This paper proposes a fast system technology co-optimization (STCO) framework that optimizes power, performance, and area (PPA) for next-generation IC design, addressing the challenges and opportunities presented by novel materials and device architectures. We focus on accelerating the technology level of STCO using AI techniques, by employing graph neural network (GNN)-based approaches for both TCAD simulation and cell library characterization, which are interconnected through a unified compact model, collectively achieving over a 100X speedup over traditional methods. These advancements enable comprehensive STCO iterations with runtime speedups ranging from 1.9X to 14.1X and supports both emerging and traditional technologies.

Chiplet-based systems have gained significant attention in recent years due to their low cost and competitive performance. As the complexity and compactness of a chiplet-based system increase, careful consideration must be given to microbump assignments, interconnect delays, and thermal limitations during the floorplanning stage. This paper introduces RLPlanner, an efficient early-stage floorplanning tool for chiplet-based systems with a novel fast thermal evaluation method. RLPlanner employs advanced reinforcement learning to jointly minimize total wire-length and temperature. To alleviate the time-consuming thermal calculations, RLPlanner incorporates the developed fast thermal evaluation method to expedite the iterations and optimizations. Comprehensive experiments demonstrate that our proposed fast thermal evaluation method achieves a mean absolute error (MAE) of$\pm 0.25$K and delivers over$120\mathrm{x}$speed-up compared to the open-source thermal solver HotSpot. When integrated with our fast thermal evaluation method, RLPlanner achieves an average improvement of 20.28% in minimizing the target objective (a combination of wirelength and temperature), within a similar running time, compared to the classic simulated annealing method with HotSpot.

Flexible hybrid electronics (FHE), integrating high performance silicon chips with multi-functional sensors and actuators on flexible substrates, can be intimately attached onto irregular surfaces without compromising their functionalities, thus enabling more innovations in healthcare, internet of things (IoTs) and various human-machine interfaces (HMIs). Recent developments on compact models and process design kits (PDKs) of flexible electronics have made designs of small to medium flexible circuits feasible. However, the absence of a unified model and comprehensive evaluation benchmarks for flexible electronics makes it infeasible for a designer to fairly compare different flexible technologies and to explore potential design options for a heterogeneous FHE design. In this paper, we present AutoFlex, a unified evaluation and design framework for flexible hybrid electronics, where device parameters can be extracted automatically and performance can be evaluated comprehensively from device levels, digital blocks to large-scale digital circuits. Moreover, a ubiquitous FHE sensor acquisition system, including a flexible multi-functional sensor array, scan drivers, amplifiers and a silicon based analog-to-digital converter (ADC), is developed to reveal the design challenges of a representative FHE system.

Large area flexible electronics (FE) is emerging for low-cost, light-weight wearable electronics, artificial skins and IoT nodes, benefiting from its low-cost fabrication and mechanical flexibility. How-ever, the low temperature requirement for fabrication on a flexible substrate and the large-area nature of flexible sensor arrays inevitably result in inadequate device yield, reliability and stability. Therefore, it is essential to develop design methodologies for large area sensing applications which can ensure system robustness with-out relying on highly reliable devices. Based on the observation that most signals sensed by body sensor arrays exhibit sparse statistical characteristics, we propose a system design method which lever-ages the sparse nature via compressed sensing (CS). Specifically, we use flexible circuitry to implement a CS encoder and decode the compressed signal in the silicon side. As a system demonstration, we fabricated the temperature sensor array, shift register and amplifier to illustrate the feasibility of the encoder design using carbon-nanotube-based flexible thin-film transistors. To evaluate the improvement of system robustness achieved by the proposed sensing schema, we conducted two case studies: temperature imaging and tactile-sensor based object recognition. With ~10% sparse errors (due to either device defects or transient errors), we achieved reduction of root-mean-square-error (RMSE) from 0.20 to 0.05 for temperature sensing and boost the classification accuracy from 65% to 84% for tactile-sensing based object recognition.

Skin-inspired electronics emerges as a new paradigm due to the increasing demands for conformable and high-quality skin-sensor-silicon (SSS) interfacing in wearable, electronic skin and health monitoring applications. Advances in ultra-thin, flexible, stretchable and conformable materials have made skin electronics feasible. In this paper, we prototyped an active electrode (with a thickness ≤ 2 um), which integrates the electrode with a thin-film transistor (TFT) based amplifier, to effectively suppress motion artifacts. The fabricated ultra-thin amplifier can achieve a gain of 32 dB at 20 kHz, demonstrating the feasibility of the proposed active electrode. Using atrial fibrillation (AF) detection for electrocardiogram (ECG) as an application driver, we further develop a simulation framework taking into account all elements including the skin, the sensor, the amplifier and the silicon chip. Systematic and quantitative simulation results indicate that the proposed active electrode can effectively improve the signal quality under motion noises (achieving ≥30 dB improvement in signal-to-noise ratio (SNR)), which boosts classification accuracy by more than 19% for AF detection.

High-performance low-cost flexible hybrid electronics (FHE) are desirable for internet of things (IoT). Carbon-nanotube (CNT) thin-film transistor (TFT) is a promising candidate for high-performance FHE because of its high carrier mobility (25cm2/V.s), superior mechanical flexibility/stretchability, and material compatibility with low-cost printing and solution processes. Flexible sensors and peripheral CNT-TFT circuits, such as decoders, drivers and sense amplifiers, can be printed and integrated with thinned (<;50μm) silicon chips on soft, thin, and flexible substrates for appealing product designs and form factors. Here we report: 1) process design kit (PDK) to enable FHE design automation, from device modeling to physical verification, and 2) open-source and solution-process proven intellectual property (IP) blocks, including Pseudo-CMOS [1] digital logic and analog amplifiers on flexible substrates, as shown in Figure 1. The proposed FHE-PDK and circuit design IP are fully compatible with silicon design EDA tools, and can be readily used for co-design with both CNT-TFT circuits and silicon chips.

Flexible Electronics (FE) is emerging for wearables and low-cost internet of things (IoT) nodes benefiting from its low-cost fabrication and mechanical flexibility. Combining FE with thinned silicon chips, known as flexible hybrid electronics (FHE), can take advantages of both low-cost printed electronics and high performance silicon chips. To design a FHE system, the process design kit (PDK) offering the capabilities for circuit design, simulation and verification for both FE and silicon chips is needed. The key elements of FHE-PDK include technology files for design rule checking (DRC), layout versus schematic (LVS) and layout parasitics extraction (LPE), as well as SPICE-compatible models for flexible thin-film transistors (TFTs) and passive elements. Wafer scale measurements are used to validate our SPICE models and design rules are derived accordingly to assure a satisfactory yield. With FHE-PDK, circuit and system designers can therefore focus on design innovations and can rely on design tools to produce manufacturable designs.

Carbon nanotube thin film transistor (CNT-TFT) is a promising candidate for flexible electronics, because of its high carrier mobility and great mechanical flexibility. An accurate and trustworthy device model for CNT-TFTs, however, is still missing. In this paper, we present a SPICE-compatible compact model for CNT-TFT circuit simulation and validate the proposed model based on fabricated CNT-TFTs and Pseudo-CMOS circuits [1][2]. The proposed CNT-TFT model enables circuit designers to explore design space by adjusting device parameters, supply voltages and transistor sizes to optimize the noise margin (NM) and power-delay product (PDP), which are the key merits for larger scale CNT-TFT circuits. We further propose a design framework to effectively optimize the NM and PDP to facilitate greater automation of flexible circuit design based on CNT-TFTs.

Flexible electronics is promising for a number of emerging applications such as foldable smartphone, wearables and internet of things (IoT) [1], [2], [3]. However, the key elements of flexible electronics, the thin-film transistors (TFT), often suffer from large process variations and inferior reliability. There is also a lack of trustworthy compact models for these devices. This paper gives an overview of design challenges for the flexible circuits, introduces a robust design style, Pseudo-CMOS, that has been widely used for digital TFT designs, and highlights the development of a flexible hybrid electronics process design kit (FHE-PDK) supporting design automation and verification of flexible hybrid electronics.