Strong Physical Unclonable Functions (PUFs) have gained traction as lightweight authentication solutions for IoT devices. However, their vulnerability to machine learning attacks poses a security risk. Various strategies have been introduced in the literature to enhance its resilience against modeling attacks, introducing additional complexity and making them unsuitable for resource-constrained devices. In contrast, weak PUFs exhibit inherent resistance to modeling attacks, but they suffer from a restricted number of Challenge-Response Pairs (CRPs), thus unsuitable for authentication. This paper proposes a PUF design that incorporates weak PUFs to obscure the responses of Strong PUFs, effectively safeguarding them from modeling attacks. Our design shows resilience against a modeling attack, revealing a maximum accuracy of 57% despite using 107CRPs. The proposed method is implemented on the Artix-7 FPGA with Verilog HDL. The results demonstrate that the proposed method has a small footprint in terms of resource utilization. This innovative approach offers a lightweight solution for IoT device authentication, combining the strengths of strong and weak PUFs while mitigating the vulnerabilities associated with modeling attacks.

Physically Unclonable Functions (PUFs) are hardware security primitives that can offer an alternative lightweight security solution for authenticating constrained Internet of Things (IoT) devices. However, PUFs are susceptible to modeling attacks, requiring the adoption of various design approaches to increase their resiliency. Many research efforts propose design approaches that offer better security against modeling attacks. This work investigates state-of-the-art modeling attacks performed on well-known Arbiter-based PUF architectures highlighting the best-fit modeling algorithm for different design approaches. Furthermore, the area efficiency of studied PUF designs is examined, and the optimal PUF design approaches for various area constraints are suggested. Such an assessment is required to evaluate PUF security accurately and guide the PUF community toward better practices. The findings revealed that some machine-learning algorithms performed better on a particular design. Additionally, when considering area overhead, we found that some PUF designs offer less security per area unit than their simpler counterparts. Accordingly, certain design elements are more efficient and add more security.

Physical unclonable functions (PUFs) are hardware security primitives that offer a lightweight security solution for constrained devices in the Internet of Things. The challenges facing PUFs security scaling have so far hindered their wide-scale deployment beyond simple key generation primitives. Although physically unclonable, PUFs are vulnerable to soft modeling attacks. Many PUF security enhancements impose significant implementation overhead, which could be problematic for devices operating in a constrained environment. This work introduces the Cross-Feed (XFeed) PUF, a highly efficient PUF circuit resilient against machine learning attacks while requiring a small circuit implementation area. In the XFeed PUF, arbiters feed intermediate race conditions to adjacent PUF rows to increase the non-linearity of the PUF system. A systematic categorization and benchmarking of the possible interconnection strategies are performed to determine the near-optimal connection schemes for the introduced XFeed PUF. The results showed that the XFeed PUF has superior security efficiency and scalability compared to other arbiter PUF-based enhancements.

Physical Unclonable Functions (PUFs) are popular hardware security primitives that offer lightweight authentication for constrained devices. However, lightweight PUF-based authentication often limits the number of authentications provided or even throttle the device to prevent adversaries from collecting enough information that could compromise the device’s security. This work introduces a Shadow PUF design, a controlled Strong PUF, to secure challenge-response exchanges against attackers and allow for an unlimited generation of unique responses. The proposed Shadow PUF design ensures security by periodically reconfiguring its behavior. The reconfiguration bits are generated by a static PUF primitive and are never exposed, while all authentication exchanges are done using the reconfigurable Shadow PUF. An ASIC Synthesis of the Shadow PUF demonstrates its small implementation area requirements and low power consumption. The security of the proposed PUF design against modeling attacks has also been analyzed.

Challenges in securing the Internet of Things (IoT) has led to the development of novel technologies such as physically unclonable functions (PUFs). Having applications in both lightweight authentication and key generation protocols for IoT devices, PUFs have received a great deal of research. Despite their promise, delay-based PUFs such as Arbiter PUFs and 4-XOR PUFs are easily modeled with 600 and 50, 000 challenge-response pairs (CRPs), respectively. While it has been shown that delay-based PUFs can be further improved by XORing together an increasing number of PUF instances, it also tends to become area-inefficient. In this paper the authors propose a novel method that combats the effectiveness of machine learning algorithms for modeling PUF behaviors by randomly selecting responses from a pool of PUFs. Six variants to our Random Bit Selection (RBS) PUF are proposed and investigated. The yielded results show that specific variants of RBS PUF are machine learning resistant despite using a 5, 760, 000 CRP dataset for training. Furthermore, the results indicate no significant improvement in the modeling algorithm despite a 100 times increase in the number of CRPs used. Finally, the security of the proposed design is also evaluated through a brute-force analysis to show its resistance to brute-force attacks.

This paper presents a high speed architecture of a recently proposed compressive sensing detection method for wideband cognitive radios using least squares. Using least squares instead of the orthogonal matching pursuit for signal recovery reduces the computational complexity where, the index search and matrix inverse stages are avoided. The proposed architecture is fully pipelined where, 14 clock cycles are required to detect 1024-length signal occupying 8 channels from 16 measurements. The design is implemented in 45 nm CMOS operating at 165 MHz. Since, the sensing time for 1024-length signal is roughly 84.8 ns, the proposed design offers high speed signal detection compared with state of art orthogonal matching pursuit architecture.