To solve the high bit error rate (BER) problem of conventional 56-Gb/s nonreturn-to-zero (NRZ) transceivers under high-insertion loss (IL) channels, this study proposes a high-speed adaptive duobinary (DB) digital detector based on the feed-forward equalizer (FFE) and the maximum likelihood sequence detector (MLSD). In this detector, adaptive FFE is combined with channel characteristics to generate DB signals and complete equalization, thus extending the transmission bandwidth and eye height and allowing a larger sampling phase offset. The parallel MLSD is used to complete the detection and decoding of DB signals to reduce the BER. An adaptive algorithm is proposed to avoid the long convergence time of the conventional zero-forcing (ZF) algorithm applied to the DB detector, so that it can be applied to various bit rates and IL channels. In this study, the verification of this DB detector is accomplished at 56 Gb/s. The platform based on a 56-Gb/s analog front-end chip (AFEC) and field-programmable gate array (FPGA) proves that the detector can work well in 12–56 Gb/s and multiple IL channels. The BER was less than 2e-8 at 56 Gb/s on −42-dB channel loss at 28 GHz. The structure can be well used for higher rate transceivers, such as 112 Gb/s.

Long DRAM access latency has a significant impact on modern system performance. However, the improvement of DRAM access latency is limited, as the DRAM vendors reserve considerable timing margins against seldom worst-case conditions. To mitigate such pessimistic timing margins, we propose a temperature- and process-variation-aware timing detection and adaption DRAM (TPDA-DRAM) architecture. It equips in-situ cross-coupled detectors to monitor the voltage difference between bitline pairs, enabling estimation of timing margins caused by process and temperature variations. Moreover, TPDA-DRAM incorporates two collaborative timing adaption schemes: 1) a process-variation-aware timing adaption scheme (PVA) that selectively accelerates the access to weak cells, and 2) a temperature-variation-aware timing adaption scheme (TVA) that precisely adjusts timing parameters by adopting temperature information. Compared to prior art, the proposed detector reduces detection deviation by 54.8% and area overhead by 88.1%. The system-level evaluation in an eight-core system shows that TPDA-DRAM improves the average performance and energy efficiency by 20.5% and 15.0%, respectively.

The limitations of traditional von Neumann architectures and digital computing are the bottlenecks for high-speed signal processing capabilities, not to mention the explosion of information growth. To tackle this challenge, this paper proposes an artificial neural network (ANN) equalizer based on the memristor for high-speed channel transmission at 112Gbps with 4-level pulse amplitude modulation (PAM4). To implement the PAM4 signal decision circuit based on the softmax algorithm, a comparator is used to make binary decisions for each output, and the only high-level output is further selected for the decision-making. The simulations on the PSPICE platform reveal that the number of input taps and the location of the main tap have the greatest impact on bit error rate (BER) performance. With optimal parameters, the circuit can achieve an impressive BER performance as low as 3.45E-6. To the best of our knowledge, this is the first implementation of channel equalization using memristive circuits, providing a valuable reference for analog circuit implementations of neural network equalizers.

Interconnect Network is the key component in high performance computing system. With the incoming era of Exa-Scale (1018FLOPS) computing, designing large scale interconnect networks is facing with serious challenges in network management and fault tolerance. To construct higher performance and more reliable interconnect networks, we propose an efficient and intelligent network management architecture for indirect interconnect networks. This paper emphatically introduces the network management architecture, the in-band management channels in the Network Interface Chips (NIC) and Network Routing Chips (NRC) respectively, efficient centralized network management approach, distributed intelligent faulttolerant routing management, and so on. Based on the prototype system, the Control and Status Registers (CSR) accessing latency performance of in-band network management is evaluated. Also based on a customized simulation model for indirect interconnect networks, the typical distributed fault-tolerant scenes are tested. The experiment results show the in-band network management can averagely achieves 716 times improvements than the out of-band network management. Moreover, by running heuristic algorithms to automatically reconstruct routing tables for failure links or routers, the intellectual network management Engine can achieve fault-tolerant routing to maximizing network performance.

An on-chip optical transceiver for transmission system over 100GBd is proposed based on optical time division multiplexing (OTDM) technology, and the performances, such as the insertion loss, the inter-symbol interference (ISI) crosstalk, and the potential symbol rate, are analyzed in detail. Co-designed with the double rail driver, on-chip Mach-Zehnder interferometer switch repeatedly generates extremely narrow sampling pulses of only 12ps full width at half maximum. Based on such narrow optical sampling pulse train, a four-stage cascaded optical switch divides the 25GHz clock cycle into four recurrent 9.5ps time slots and one blank time slot of 2ps. Thus, a 100GBd optical transmission channel is realized based on 4-bit 25Gbps bit-streams at the electrical interface. The ISI extinction ratio at the worst channel is 1.9dB with 10dB depth modulator, and the insertion loss caused by the OTDM mechanism is about 16dB. Further, taking advantages of dark modulation, an OTDM system with 5-bit 25Gbps bit-streams at the electrical interface is proposed to generate a 125GBd transmission utilizing the same optical sampling pulse. The ISI performance is much better and the extinction ratio at the worst channel is enhanced to 3.99dB.

In this paper, we propose FlyCast, an architecture using the physical layer of free-space optics (FSO) to accelerate multicast communication. FlyCast leverages off-the-shelf devices (e.g. switchable mirror, beam splitter) to physically split the FSO beam to multi receivers on demand, which enables to build dynamical multicast trees in physical layer and accelerates multicast communications. We demonstrate the feasibility of FlyCast through our theoretical analysis and the proof-of-concept prototype.