Digital Circuits are extremely vulnerable to reverse engineering which can reveal the design and functionality of an integrated circuit (IC) and expose valuable intellectual property (IP). A solution to this problem is to use different IC camouflaging techniques or gates to hinder the attacker’s ability to discover the functionality of the design. One type of camouflaged gate is the Threshold Voltage Defined (TVD) logic family. This gate type uses different threshold voltage transistors to disguise the functionality of the circuit. One of the drawbacks of the TVD logic family is that it is a synchronous logic family which makes it extremely vulnerable to Logic Laser State Imaging (LLSI) Attacks. This paper proposes using handshaking logic to create an asynchronous version of the TVD logic family to remove its vulnerability to LLSI attacks and to increase the speed of the TVD gates.

Physical attacks on secure devices can leak sensitive data and have significant consequences for individuals, companies, and governments. Today, much research is centered around understanding hardware weaknesses and vulnerabilities and, in turn, designing countermeasures to increase system security. One such countermeasure is the implementation of the camouflaging gate called PG-TVD (pass gate-based threshold voltage defined), which ensures protection against reverse engineering and sidechannel attacks. However, proper investigation is needed to determine if the countermeasure opens the door to other powerful attacks, such as laser fault injection (LFI) attacks. Identifying the vulnerability against this attack requires a proper assessment. As the first attempt to understand laser sensitivity in PG-TVD, we develop a workflow for assessing a circuit layout's sensitivity to LFI. We use this workflow to analyze the PG-TVD, giving the laser-sensitive areas. A deeper understanding of how to protect devices can be gained from this assessment to keep sensitive data secure. From the information obtained by our workflow, we also propose, design, and simulate a mitigation scheme that mitigates the laser sensitivity in PG-TVD logic cells by approximately 83%.

This paper presents a new correlated level shifting (CLS) technique that relaxes the design criteria for the residue amplifier in pipelined successive approximation register (SAR) ADCs. Unlike prior techniques, this correlated level shifting technique does not load the residue amplifier during its initial estimation phase by sampling its output to generate an estimate for use in level-shifting. Instead, the estimate is generated by using the residue voltage stored on the SAR DAC to create a look-ahead path that charges the level-shifting and load capacitors before the start of amplification. The operation of the look-ahead CLS (LACLS) technique is described and its effect on key residue amplifier design criteria such as slew rate, linear output range, and dc gain is analyzed. Simulation results are provided to verify the technique in the context of a pipelined SAR ADC and a discussion is given on choosing an appropriate circuit-level implementation for the look-ahead path. Finally, the merits of look-ahead correlated level shifting are discussed and compared to other techniques.