Processing-in-memory (PIM) paradigm is a promising solution to minimize the cost of data movement in the von Neumann architecture. Many proposals have explored possibilities to realize this paradigm in the main memory leveraging DRAM technologies. DRAM-based PIM technology can be implemented in two ways: processing-in-memory with digital compute units in peripheral area and processing-using-memory (PUM). Although computing within memory cells without digital compute units at peripherals is certainly appealing, DRAM-based PUM architectures still have various limitations to overcome. In particular, we identify three major challenges to bring PUM closer to production: compatibility with commodity DRAM microarchitecture, reliability, and coverage of operations. To address these challenges, we propose PRADA, a Processing-using-Memory Architecture based on DRAM cell Array. Unlike existing proposals, PRADA does not introduce any changes to the highly optimized cell area by not utilizing either designated rows for computation or dual-contact cells (DCCs) to implement NOT operation. Instead, PRADA proposes two new states in the bitline sense amplifier (BLSA) to implement NOT operation without any new additional circuitry. We also demonstrate how to implement various operations in PRADA, not only bit-wise logical operations but also both integer (INT) and floating-point (FP) arithmetic operations, while ensuring reliable bitline (BL) sensing. Compared to state-of-the-art PUM architectures, PRADA demonstrates 2.67--4.79× higher throughput for 8-bit integer multiply. For vector-ADD, PRADA achieves 3.09--3.13× speedups over the baseline, outperforming the other PUM architectures which show 1.04--2.07× speedups, while maintaining superior compatibility and reliability.

For efficient DNN inference Resistive RAM (ReRAM) crossbars have emerged as a promising building block to compute matrix multiplication in an area- and power-efficient manner. To improve inference throughput sparse models can be deployed on the ReRAM-based DNN accelerator. While unstructured pruning maintains both high accuracy and high sparsity, it performs poorly on the crossbar architecture due to the irregular locations of pruned weights. Meanwhile, due to the non-ideality of ReRAM cells and the high cost of ADCs, matrix multiplication is usually performed at a fine granularity, called Operation Unit (OU), along both wordline and bitline dimensions. While fine-grained, OU- based row compression (ORC) has recently been proposed to increase weight compression ratio, significant performance potentials are still left on the table due to sub-optimal weight mappings. Thus, we propose a novel weight mapping scheme that effectively clusters zero weights via OU-level filter reordering, hence improving the effective weight compression ratio. We also introduce a weight recovery scheme to further improve accuracy or compression ratio, or both. Our evaluation with three popular DNNs demonstrates that the proposed scheme effectively eliminates redundant weights in the crossbar array and hence ineffectual computation to achieve 3.27--4.26× of array compression ratio with negligible accuracy loss over the baseline ReRAM-based DNN accelerator.

In-memory computing is rapidly rising as a viable solution that can effectively accelerate neural networks by overcoming the memory wall. Resistive RAM (RRAM) crossbar array is in the spotlight as a building block for DNN inference accelerators since it can perform a massive amount of dot products in memory in an area- and power-efficient manner. However, its in-memory computation is vulnerable to errors due to the non-ideality of RRAM cells. This error-prone nature of RRAM crossbar limits its wordline-level parallelism as activating a large number of wordlines accumulates non-zero current contributions from RRAM cells in the high-resistance state as well as current deviations from individual cells, leading to a significant accuracy drop. To improve performance by increasing the maximum number of concurrently activated wordlines, we propose two techniques. First, we introduce a lightweight scheme that effectively eliminates the current contributions from high-resistance state cells. Second, based on the observation that not all layers in a neural network model have the same error rates and impact on the inference accuracy, we propose to allow different layers to activate non-uniform numbers of wordlines concurrently. We also introduce a systematic methodology to determine the number of concurrently activated wordlines for each layer with a goal of optimizing performance, while minimizing the accuracy degradation. Our proposed techniques increase the inference throughput by 3-10× with a less than 1% accuracy drop over three datasets. Our evaluation also demonstrates that this benefit comes with a small cost of only 8.2% and 5.3% increase in area and power consumption, respectively.

Object serialization and deserialization (S/D) is an essential feature for efficient communication between distributed computing nodes with potentially non-uniform execution environments. S/D operations are widely used in big data analytics frameworks for remote procedure calls and massive data transfers like shuffles. However, frequent S/D operations incur significant performance and energy overheads as they must traverse and process a large object graph. Prior approaches improve S/D throughput by effectively hiding disk or network I/O latency with computation, increasing compression ratio, and/or application-specific customization. However, inherent dependencies in the existing (de)serialization formats and algorithms eventually become the major performance bottleneck. Thus, we propose Cereal, a specialized hardware accelerator for memory object serialization. By co-designing the serialization format with hardware architecture, Cereal effectively utilizes abundant parallelism in the S/D process to deliver high throughput. Cereal also employs an efficient object packing scheme to compress metadata such as object reference offsets and a space-efficient bitmap representation for the object layout. Our evaluation of Cereal using both a cycle-level simulator and synthesizable Chisel RTL demonstrates that Cereal delivers 43.4× higher average S/D throughput than 88 other S/D libraries on Java Serialization Benchmark Suite. For six Spark applications Cereal achieves 7.97× and 4.81× speedups on average for S/D operations over Java built-in serializer and Kryo, respectively, while saving S/D energy by 227.75× and 136.28×.

Subway is one of the public transport which carries people at the exact time. In the metropolis all over the world, it transfers countless people in the rush hour. Since there is no traffic jam in the subway, accuracy is one of the most crucial characters of the subway. However, subway trains are often delayed by some reasons like an accident. The delay can make many people confused and inconvenient. In this context, the need for dynamic timetable model which corrects the error of timetable in real time has emerged. Since the method to detect train moving is necessary to modify timetable, various solutions are proposed in the indoor positioning way, such as Wi-Fi fingerprint, magnetometer and so on. A method using Wi-Fi fingerprint is a primary way in indoor positioning, but it is tough to build a radio map for every single station. Shin et al. suggested a solution using a magnetometer, with simple judging criteria named 'decision peak.' This research proved that a magnetometer is a practical solution. Nonetheless, it can not detect the train moving in some cases. We propose a new method to detect the subway moving using a linear accelerometer, based on the essence of the problem.