This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.

This paper presents a PVT-robust, high gain range and high linearity analog baseband (ABB) circuit for wideband communication. The ABB circuit consists of a four-stage programmable gain amplifier (PGA) and an embedded second-order low pass filter (LPF). In order to satisfy the PVT variations, a novel PGA topology based on two-stage miller OTA with self PVT compensation and dynamic pole-capturing technique is proposed. Besides, the ABB circuit uses floating-bulk bias method to achieve high linearity. Fabricated in 28-nm CMOS process, the measurement results show that the ABB circuit can provide a programmable gain range from 0 to 40 dB with 6 dB coarse and 1 dB fine step, while the 3 dB bandwidth greater than 550 MHz. It obtains an OP1dBof 5dBm and OIP3 of 26.1dBm for the maximum gain state. The ABB circuit occupies a core area of 0.23 mm2and consumes a DC power consumption of 15 mW from 0.9-V supply.

This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.