EDBT 2026 Demo / reviewers in the wild / expert
Shiqiang Yu
dblp:166/9802
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 78% Parallel and multicore computing · 12% GPUs and heterogeneous computing · 10% |
Topics — the 6 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
performance diagnosis |
0.3 | 1 | 2017 | VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-Core · IEEE Trans. Parallel Distributed Syst. 2017 |
Performance modeling and evaluation
performance variability |
0.3 | 1 | 2017 | VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-Core · IEEE Trans. Parallel Distributed Syst. 2017 |
Concurrent programming › concurrency bug detection
atomicity violation detection |
0.2 | 1 | 2016 | Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures · IEEE Trans. Computers 2016 |
Concurrent programming
concurrency bug detection |
0.2 | 1 | 2016 | Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures · IEEE Trans. Computers 2016 |
Concurrent programming › concurrency bug detection
data race detection |
0.2 | 1 | 2016 | Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures · IEEE Trans. Computers 2016 |
GPUs and heterogeneous computing › CPU-GPU heterogeneous computing
fused CPU-GPU architecture |
0.1 | 1 | 2016 | Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU Architectures · IEEE Trans. Computers 2016 |
Methods — techniques the papers use, named apart from their topics
trace collection · 0.5happens-before relation · 0.5bloom filter · 0.5statistical inference · 0.3clustering · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | VarCatcher: A Framework for Tackling Performance Variability of Parallel Workloads on Multi-CoreabstractThe non-deterministic nature of multi-threaded workloads running on multi-core platforms often leads to notable performance variability from run to run. Such variability makes experimental results prone to misinterpretations or misguided claims. To deal with such variability, statistical inference methods are usually used to summarize the experimental results with certain confidence levels by running the experiments or measurements a large number of times. However, such statistical results are often too vague or too simplistic. They are not sufficient to help users understand the causes of such variability, and allow more in-depth analysis on the results or reproduce the results for validation during design space exploration. To allow better analyzability and reproducibility, we propose a framework to tackle such variability, called VarCatcher. The key to VarCatcher is to characterize a parallel execution using Parallel Characteristics Vector (PCV). A clustering-based approach is then used to group runs with similar execution characteristics that can later be used to analyze results in-depth, to customize different evaluation strategies, reproduce the result for variability, to determine the impact of features, or to assist performance diagnosis. We have built a prototype of VarCatcher that includes a user-level toolset for runtime monitoring and measurements using the Intel Processor Trace feature on commodity Intel processors as well as an architecture extension with very low runtime overheads (around 3 and 0.01 percent accordingly). Several case studies confirm that VarCatcher enables several appealing features such as in-depth result analysis, customized evaluation strategies, and reproducibility. Xiaofeng Ji, Shiqiang Yu, Haibo Chen 0001, Tao Li 0006, Pen-Chung Yew, Wenyun Zhao |
IEEE Trans. Parallel Distributed Syst. | 4 |
| 2016 | Hardware Support for Concurrent Detection of Multiple Concurrency Bugs on Fused CPU-GPU ArchitecturesabstractDetecting concurrency bugs, such as data race, atomicity violation and order violation, is a cumbersome task for programmers. This situation is further being exacerbated due to the increasing number of cores in a single machine and the prevalence of threaded programming models. Unfortunately, many existing software-based approaches usually incur high runtime overhead or accuracy loss, while most hardware-based proposals usually focus on a specific type of bugs and thus are inflexible to detect a variety of concurrency bugs. In this paper, we propose Hydra, an approach that leverages massive parallelism and programmability of fused CPU-GPU architectures to simultaneously detect multiple concurrency bugs in threaded software, including data race, atomicity violation and order violation. Hydra extends contemporary fused CPU and GPU by introducing two modules: 1) a trace collecting module (TCM) that instruments and collects program behavior on CPU; 2) a trace preprocessing module (TPM) that processes and then transfers the traces to GPU for bug detection. Furthermore, Hydra exploits three optimizations to improve speed and accuracy, which includes: 1). using the bloom filter to filter out unnecessary traces; 2). avoiding eviction of shared traces; 3). comparing only last-write traces for shared data with the happens-before relation. Hydra incurs small hardware complexity and requires no changes to internal critical-path processor components such as cache and its coherence protocol, and is with about 1.1 percent hardware overhead under a 32-core configuration. Experimental results show that Hydra only introduces about 0.18 percent overhead on average for detecting one type of bugs and 0.46 percent overhead for simultaneously detecting multiple bugs, yet with the similar detectability of a heavyweight software bug detector (e.g., Helgrind). Shiqiang Yu, Haojun Wang, Zhuofang Dai, Haibo Chen 0001 |
IEEE Trans. Computers | 2 |