Network intrusion detection systems are essential for defending recent computer networks from ever-evolving cyberattacks. Security is of utmost importance due to the complex and constantly changing nature of network threats. To improve the detection capabilities in network traffic, this research presents a unique method for intrusion detection by utilizing attention-based transformer architectures. The proposed Transformer-based model offers an adaptable and reliable method for detecting sophisticated and dynamic threats by fusing the strength of the self-attention mechanism. The model is evaluated on two network intrusion benchmark datasets (NSL-KDD, UNSW-NB15). The correlation technique is used for feature extraction, and both binary and multi-class classification with and without feature extraction are performed on the datasets. The proposed model achieved over 99% accuracy, precision, and recall on the two datasets. The experimental results indicate that the proposed approach provides better results than other systems.

VLSI Designs are getting more complex with the advancements in technologies. These design rules are forcing a large number of components on a single chip. The number of registers is also increasing in SOC/IP designs. The conventional verification techniques fail to provide consistent results when design consists of a large number of registers. The proposed architecture establishes a platform to automate the verification of complex intellectual properties with multiple register access. It improvises the results as compared to SystemVerilog and conventional Universal Verification Technology (UVM) testbench. This paper focuses on advanced verification scenarios using coverage automation and Register Access Technology (RAT) on UVM verification environment. The proposed testbench automation incorporates all necessary attributes including the functional correctness of register values. The work exposes the register database in multiple register SoC/IP design. The proposed testbench justifies the functional coverage and fast execution of verification flow as compared to conventional verification methods.