Integrating domain-specific hardware accelerators on modern systems on chips (SoCs) has enabled complex applications, such as vision, natural language processing, autonomous driving, and augmented reality, on small form factors. This leads to challenges in the integration of accelerators, with high memory bandwidth requirements and strict deadlines, on the system’s memory hierarchy. The system-level shared cache, or last-level cache (LLC), is a critical resource shared by multi-core processors, GPUs, and hardware accelerators in modern heterogeneous SoCs. It significantly reduces the bottleneck at the off-chip memory and delivers high performance. With the integration of accelerators on the LLC gaining momentum, the on-chip shared cache management becomes vital. If not managed intelligently, the interference between cache requests from the cores and the accelerators can significantly deteriorate their performance. Given the architectural differences between DRAM and cache systems, the off-chip memory management strategies explored by previous works cannot be extended to the LLC. We propose a deadline-aware flexible LLC arbitration and scheduling framework, FLASH , to dynamically partition the LLC bandwidth between the accelerators and multi-core processors to meet the deadline given for the accelerator while minimizing the impact on the performance of the cores. FLASH arbitrates between the requests from the cores and the accelerators and schedules the requests depending on the accelerator’s progress and its chances of meeting the deadline. We evaluate FLASH across different workloads and hardware accelerator configurations to show that it not only achieves significantly better performance for the cores than other static scheduling policies but also significantly reduces the deadline miss rates of the accelerator.

To keep up with the growing computational demands of current-day applications, SoC design has shifted towards heterogeneous architectures with CPUs and domain-specific accelerators. These accelerators demand high on-chip and off-chip memory bandwidth and require efficient management of shared system resources. We characterize Internet Protocol Security (IPsec), a high-throughput application, by collecting the memory traces of this application running on the accelerators and CPU cores of NXP LX2160A SoC. We use this characterization to design a simulation infrastructure for simulating IPsec on possible domain-specific architectural extensions and perform a design-space exploration across various general-purpose memory management policies. We propose APPAMM, an application-specific predictive packet-aware memory management policy using the knowledge of IPsec to improve performance for next-generation SoCs. Using our approach to manage memory for different input packet streams, we report improvements of up to 22x in the packet drop rate and peak throughput.

Recently a prominent attack vector called Volt Boot attack was disclosed, which exploits low power mode (i.e., power gating) transitions and power distribution networks of SoCs, to compromise the content of on-chip SRAMs with higher data accuracy than traditional cold boot attacks. This attack can compromise on-chip SRAMs that store plaintext data for subsequent processing. The present mitigation techniques either incur longer latency or increase the area/power of the SoC. This paper proposes address and data mapping/de-mapping with different true random number generators(TRNG). These TRNGs are used to map/de-map the address and data to newer values in the memory array when the boot/reset/power or tampering event is detected. Any memory read/write request is served after mapping/de-mapping the address/data with appropriate boolean functions using stored TRNGs. This technique changes the memory contents or traces after each boot/power cycle of SoC or tampering event with respect to the contents of previous computations. Our results show that the proposed technique makes current memory data uncorrelated to previously stored memory contents. Also, our technique shows low implementation area overhead and reduces the latency of data corruption to one clock cycle.