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Bisheng Huang

dblp:167/2981 · DBLP profile ↗
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4ranked-venue papers
0as first author
2since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 since 2021Artificial intelligence and machine learning · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Storage systems · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems
flash and SSD
1.012026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026
Storage systems › flash and SSD › flash memory management
garbage collection
1.012026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026
Storage systems
key-value storage
1.012026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026
Storage systems › key-value storage
LSM-tree
1.012026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026
Storage systems › flash and SSD
write amplification reduction
1.012026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026
Storage systems › key-value storage
key-value separation
0.312026
HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs · ACM Trans. Archit. Code Optim. 2026

Methods — techniques the papers use, named apart from their topics

two-level index · 1.0in-place overwrite · 1.0asynchronous value flushing · 1.0
YearPublicationVenuePosition
2026 HeapKV: Enabling Efficient Garbage Collection for KV-Separated LSM Stores on Modern SSDs
abstract
Key-value (KV) separation has emerged as a pivotal solution to tackle write amplification in LSM-tree-based KV stores (LSM stores). However, the garbage collection (GC) mechanism essential for reclaiming obsolete values introduces substantial overheads: (i) Additional LSM-tree I/O operations degrade foreground performance and cause data inconsistency issues; (ii) Exacerbated write amplification arises from excessive valid data migration in update-intensive workloads. Moreover, existing GC optimization schemes fundamentally struggle to balance space overhead, write amplification, and system performance. In this article, we propose HeapKV, a high-performance KV-separated LSM store that improves GC efficiency through three key technologies: (i) A lightweight two-level index and a global garbage view decouple GC operations of value storage from the LSM-tree, eliminating additional I/O operations; (ii) A novel valid data migration scheme mitigates write amplification during space reclamation by in-place overwrites and logical data copying; (iii) SSD-conscious I/O optimizations featuring asynchronous value flushing, fast read paths and concurrent prefetching for range queries. Extensive experiments demonstrate that HeapKV achieves 40%–7.4× higher throughput under diverse workloads with lower write/space amplification, compared to other state-of-the-art KV-separated LSM stores.
Kai Lu 0002, Yuanhui Zhou, Nengjie Wang, Jiguang Wan 0001, Bisheng Huang
ACM Trans. Archit. Code Optim.5
2021 Flexible scheme for reconfiguring 2D mesh-connected VLSI subarrays under row and column rerouting
Hao Ding 0007, Junyan Qian, Bisheng Huang, Lingzhong Zhao, Zhongyi Zhai
J. Parallel Distributed Comput.3
2020 An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray
Junyan Qian, Bisheng Huang, Hao Ding 0007, Zhide Zhou, Lingzhong Zhao, Zhongyi Zhai
Integr.2
2015 An Idle-State Detection Algorithm for SSVEP-Based Brain-Computer Interfaces Using a Maximum Evoked Response Spatial Filter
abstract
Although accurate recognition of the idle state is essential for the application of brain-computer interfaces (BCIs) in real-world situations, it remains a challenging task due to the variability of the idle state. In this study, a novel algorithm was proposed for the idle state detection in a steady-state visual evoked potential (SSVEP)-based BCI. The proposed algorithm aims to solve the idle state detection problem by constructing a better model of the control states. For feature extraction, a maximum evoked response (MER) spatial filter was developed to extract neurophysiologically plausible SSVEP responses, by finding the combination of multi-channel electroencephalogram (EEG) signals that maximized the evoked responses while suppressing the unrelated background EEGs. The extracted SSVEP responses at the frequencies of both the attended and the unattended stimuli were then used to form feature vectors and a series of binary classifiers for recognition of each control state and the idle state were constructed. EEG data from nine subjects in a three-target SSVEP BCI experiment with a variety of idle state conditions were used to evaluate the proposed algorithm. Compared to the most popular canonical correlation analysis-based algorithm and the conventional power spectrum-based algorithm, the proposed algorithm outperformed them by achieving an offline control state classification accuracy of 88.0 ± 11.1% and idle state false positive rates (FPRs) ranging from 7.4 ± 5.6% to 14.2 ± 10.1%, depending on the specific idle state conditions. Moreover, the online simulation reported BCI performance close to practical use: 22.0 ± 2.9 out of the 24 control commands were correctly recognized and the FPRs achieved as low as approximately 0.5 event/min in the idle state conditions with eye open and 0.05 event/min in the idle state condition with eye closed. These results demonstrate the potential of the proposed algorithm for implementing practical SSVEP BCI systems.
Dan Zhang 0014, Bisheng Huang, Siliang Li
Int. J. Neural Syst.2