Demo Data from EDBT 2026 / reviewers in the wild / expert
Shigeru Fujii
dblp:167/4846
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 67% Processor architecture and microarchitecture · 33% | |
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 50% Debugging and program repair · 50% |
Topics — the 3 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › special-purpose processor
digital signal processor |
0.0 | 1 | 1985 | A High Performance LSI Digital Signal Processor for Communication · IEEE J. Sel. Areas Commun. 1985 |
Integrated circuit design › digital arithmetic circuits › integer multiplier
high-speed multiplier |
0.0 | 1 | 1985 | A High Performance LSI Digital Signal Processor for Communication · IEEE J. Sel. Areas Commun. 1985 |
Integrated circuit design › digital circuit design › arithmetic circuit design
multiplier design |
0.0 | 1 | 1985 | A High Performance LSI Digital Signal Processor for Communication · IEEE J. Sel. Areas Commun. 1985 |
Methods — techniques the papers use, named apart from their topics
memory capacity analysis · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | A High Performance LSI Digital Signal Processor for CommunicationabstractThis paper describes a newly developed CMOS LSI DSP (FDSP3). It has a powerful multiplier, which operates at a rate of 10 M-operations/s, almost twice as fast as the fastest existing LSI DSP's. Some key techniques to attain these high performance characteristics of the DSP are described. Suitable memory capacities of the RAM and ROM were analyzed as a function of the operational capability of the DSP. These were reflected in the design of the FDSP3. To assist in the development of the program, support tools have been developed. A Pascal based cross compiler and an on-line debugging tool are described in some detail. Yukou Mochida, Kazuo Murano, Toshitaka Tsuda, Hirohisa Gambe, Shigeru Fujii |
IEEE J. Sel. Areas Commun. | 5 |