High interconnect bandwidth is crucial for achieving better performance in many-core GPGPU architectures that execute highly data parallel applications. The parallel warps of threads running on shader cores generate a high volume of read requests to the main memory due to the limited size of data caches at the shader cores. This leads to a scenarios with rapid arrival of an even larger volume of reply data from the DRAM, which creates a bottleneck at memory controllers (MCs) that send reply packets back to the requesting cores over the network-on-chip (NoC). Coping with such high volumes of data requires intelligent memory scheduling and innovative NoC architectures. To mitigate memory bottlenecks in GPGPUs, we first propose a novel approximate memory controller architecture (AMC) that reduces the DRAM latency by opportunistically exploiting row buffer locality and bank level parallelism in memory request scheduling, and leverages approximability of the reply data from DRAM, to reduce the number of reply packets injected into the NoC. To further realize high throughput and low energy communication in GPGPUs, we propose a low power, approximate NoC architecture (Dapper) that increases the utilization of the available network bandwidth by using single cycle overlay circuits for the reply traffic between MCs and shader cores. Experimental results show that Dapper and AMC together increase NoC throughput by up to 21 percent; and reduce NoC latency by up to 45.5 percent and energy consumed by the NoC and MC by up to 38.3 percent, with minimal impact on output accuracy, compared to state-of-the-art approximate NoC/MC architectures.

Data-snooping is a serious security threat in NoC fabrics that can lead to theft of sensitive information from applications executing on manycore processors. Hardware Trojans (HTs) covertly embedded in NoC components can carry out such snooping attacks. In this paper, we first describe a low-overhead snooping invalidation module (SIM) to prevent malicious data replication by HTs in NoCs. We then devise a snooping detection module (THANOS) to also detect malicious applications that utilize such HTs. Experimental analysis shows that unlike state-of-the-art mechanisms, SIM and THANOS not only mitigate snooping attacks but also improve NoC performance by 48.4% in the presence of these attacks, with a minimal ~2.15% area and ~5.5% power overhead.

Reliability is a major concern in chip multi-processors (CMPs) due to shrinking technology and low operating voltages. Today's processors designed at sub-10nm technology nodes have high device densities and fast switching frequencies that cause fluctuations in supply voltage (Vdd) and ground networks, which can adversely affect the execution of applications running on them. In this paper, we propose a novel runtime framework to reduce the power supply noise (PSN) in cores and routers at runtime. Experimental results for 7nm FinFET process nodes show that our framework not only achieves up to 4.5× reduction in PSN, and up to 34.3% improvement in application performance, but also manages to map up to 38% more applications when the CMP is oversubscribed, compared to the state-of-the-art.

High interconnect bandwidth is crucial to achieve better performance in many-core GPGPU architectures that execute highly data parallel applications. The parallel warps of threads running on shader cores generate a high volume of read requests to the main memory due to the limited availability of data cache space at the shader cores. This leads to scenarios with rapid arrival of reply data from the DRAM, which creates a bottleneck at memory controllers (MCs) that send reply packets back to the requesting cores over the NoC. Coping with such high volumes of data requires NoC architectures that possess high power overhead. To accomplish high bandwidth and low energy communication in GPGPUs, we propose Dapper, a data-aware approximate NoC architecture that increases the utilization of the available bandwidth by using low power single cycle overlay circuits for the reply traffic between MCs and shader cores. Dapper also incorporates a novel MC architecture that leverages the inherent approximability of the data values of certain applications and reduces the number of reply packets injected into the NoC by the MCs. Experimental results show that Dapper reduces the energy consumed in the GPGPU by up to 50% with up to 99% application output accuracy and minimum performance overheads compared to a state-of-the-art approximate NoC architectures.

Transient faults due to single and multiple bit-flips are becoming increasingly common in today's multicore processing chips and reduce overall chip reliability. Simultaneously, aging effects due to phenomena such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) also gradually reduce chip reliability over time. Unfortunately, with technology scaling, the increasingly stringent on-chip dark-silicon power constraints prohibit costly fault resilience solutions. Clearly, a viable approach is needed that can address both transient- and aging-induced faults in emerging multicore chips, but this is not easy. For example, techniques to slow down aging typically increase susceptibility to transient faults and vice-versa. In this paper, we propose a novel runtime framework (CHARM) to manage the useful chip lifetime, while also addressing transient faults and meeting performance and dark-silicon constraints. Experimental results on a 60-core chip multiprocessor show that CHARM not only achieves transient fault resilience while satisfying dark-silicon constraints, but also achieves an improvement of up to 2.5× in lifetime, and up to 6× in number of applications executed over the chip lifetime compared to a state-of-the-art solution.

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