Generally, in the telecommunication industry, VLSI implementation is viewed as a means to cost reduction and is attempted only after successively decomposing a system into circuits corresponding to individual printed circuit boards (PCB's). This traditional "circuit-design" approach is unable to cope with and to exploit the potential of VLSI capabilities such as chip density and processing power. The availability of unprecedented processing power and the recognition of "effective endproduct cost" as the true measure for VLSI chip fabrication are leading the change over from integrated circuit design to integrated system design. In this paper, this emerging system design methodology for VLSI implementation and its two elements, system partitioning and performance specification allocation, are illustrated by two design examples; one relating to line-circuit design and the other to a packet-switch design.

This paper describes the implementation of the test system of the ITT System 1240 digital switch that was developed for line, trunk, and service circuit maintenance and diagnostics. At the core of the test system is a problem-oriented, remotely programmable, digital signal processor called the test signal analyzer (TSA). The TSA is a versatile signal generation and measurement tool, whose signal processing power is made readily available to the test engineer as a set of high-level functional instructions, rather than as a primitive register transfer language, or as inflexible test-specific instructions. Specifically, this paper briefly describes the TSA implementation, identifies the functions that are fundamental to any telecommunications test system, presents some of the digital signal processing algorithms, and gives a measurement example.

The ever-increasing use of VLSI in telecommunications systems is leavening the search of new algorithms for task realizations suited to VLSI implementations of systems. Toward this search, the paper presents implementations for MF/DTMF receivers, which are based on multiplierless basic filters or primitive VLSI cells such as(1 + z^{-n}),(1 - z^{-n}), and(1 \pm z^{-n} + z^{-2n}). These implementations require parallel processing and are designed to meet the requirements of a switching system.

The paper presents a design methodology based on correspondence between performance requirements, mathematical parameters, and circuit parameters of a sigma-delta modulator. This methodology will guide a design engineer in selecting the circuit parameters based on system requirements, in translating paper design directly into LSI design, in predicting the effect of component sensitivity, and in analyzing the operations of the sigma-delta modulator. The sigma-delta modulator is viewed as a device which distributes the noise power, determined by peak SNR, over a much broader band, compared to signal bandwidth, shapes and amplifies it, and allows filtering of the out-of-band noise. The shaping and amplification are quantified by two parameters,FandP, whose product is analogous to the square of step size of a uniform coder. These two parameters are related, on one hand, to the time constants or location of zero and poles. On the other hand, inequalities are set up between performance parameters, like signal-to-noise ratio and dynamic range, andFandP.

The paper establishes a correspondence between performance requirements, mathematical parameters, and circuit parameters of a sigma-delta modulator. The sigma-delta modulator is viewed as a device which distributes the noise power over a much broader band, compared to signal bandwidth, shapes and amplifies it, and allows filtering of the out-of-band noise. The shaping and amplification are quantified by two parameters, F and P, whose product is analogous to the square of step size of a uniform coder. These two parameters are related, on one hand, to the time constants or location of zero and poles. On the other hand, inequalities are set up between performance parameters, like signal-to-noise ratio and dynamic range, and F and P.

The magnitude-squared characteristic of an ideal lowpass filter is approximated, over the finite interval [-1,1], by the ratio Φ(x)/Φ(x)+P(x) of two n-th-degree polynomials. The polynomials Φ(x) and P(x) are chosen such that the ratios P(x)/ Φ(x) and Φ(x)/P(x) approximate, in a Chebyshev sense, the zero function over the passband [xp,1] and the stopband [-1,xs], respectively. The passband and stopband form two disjoint intervals. The polynomials are iteratively determined by repeated applications of Darlington's technique for obtaining rational function generalizations of Chebyshev polynomials. The efficacy of the iterative method is demonstrated by examples.

A technique is described to approximate a linear time-invariant (LTI) system by a linear m-adic invariant (LMI) system or, equivalently, approximate a circulant matrix by a supercirculant matrix. This approximation reduces the number of multiplies required for computing cyclic convolution. Furtermore, the concepts of LMI systems are presented in a tutorial fashion. Examples are included to illustrate the efficacy of the approximation technique.

This paper describes a practical computer algorithm for the solution of constrained least-squares filtering equations. This algorithm exploits the block-Toeplitz and block-circulant properties of the filtering equations. Specifically, these properties are utilized to adapt Kutikov's and Akakai's algorithms for the solution of block-Toeplitz systems. Our approach generalizes the formulation considered by Claerbout. Furthermore, it effects substantial savings in memory storage compared to existing approaches, and is therefore well suited for solving large systems.