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S. Paul Rogerson

dblp:167/8686 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1984
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
1 paper
Optical networks · 62% Physical-layer communications · 38%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Optical networks
submarine optical systems
0.011984
An Undersea Fiber-Optic Regenerator Using an Integral-Substrate Package and Flip-Chip SAW Mounting · IEEE J. Sel. Areas Commun. 1984
Integrated circuit design › analog and mixed-signal circuits
mixed-signal circuit design
0.011984
An Undersea Fiber-Optic Regenerator Using an Integral-Substrate Package and Flip-Chip SAW Mounting · IEEE J. Sel. Areas Commun. 1984
Physical-layer communications › signal processing for communications
signal regeneration
0.011984
An Undersea Fiber-Optic Regenerator Using an Integral-Substrate Package and Flip-Chip SAW Mounting · IEEE J. Sel. Areas Commun. 1984
Physical-layer communications › synchronization
timing recovery
0.011984
An Undersea Fiber-Optic Regenerator Using an Integral-Substrate Package and Flip-Chip SAW Mounting · IEEE J. Sel. Areas Commun. 1984

Methods — techniques the papers use, named apart from their topics

flip-chip mounting · 0.0ECL-40 · 0.0
YearPublicationVenuePosition
1984 An Undersea Fiber-Optic Regenerator Using an Integral-Substrate Package and Flip-Chip SAW Mounting
abstract
A 324-Mbit/s electrical regenerator module intended for undersea optical-fiber systems is described. It has a sensitivity of 20 mV peak to peak, at which the total jitter is 3.3° rms, a low figure achieved by close attention to balance at chip and circuit board level. Timing phase adjustment is by means of a single select-on-test resistor, which enables the timing to be optimized quicker and more accurately than by conventional means. The regenerator functions are realized using four chips in the proven ECL-40 technology. This number reduces to three if a 28-pin chip carrier is used. The power consumption of these chips totals 1.3 W. The module incorporates a novel method ("flip-chip") of mounting SAW filters which is mechanically robust without the use of organic compounds, and which improves SAW performance by the virtual elimination of electromagnetic breakthrough.
Paul A. Dawson, S. Paul Rogerson
IEEE J. Sel. Areas Commun.2