EDBT 2026 Demo / reviewers in the wild / expert
Tianqiong Luo
dblp:167/9306
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2019
0000-0002-4808-5547ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Computer networks · 2 · 2 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Coding theory · 67% Information theory · 33% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 67% Memory systems · 33% | |
| Computer networks
1 paper |
Content delivery and video streaming · 100% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Information theory › network information theory › caching network
coded caching |
0.4 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Coding theory
distributed storage |
0.4 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Storage systems
data representation |
0.2 | 1 | 2016 | Spreading Modulation for Multilevel Nonvolatile Memories · IEEE Trans. Commun. 2016 |
Storage systems › flash and SSD
flash memory |
0.2 | 1 | 2016 | Spreading Modulation for Multilevel Nonvolatile Memories · IEEE Trans. Commun. 2016 |
Memory systems
non-volatile memory |
0.2 | 1 | 2016 | Spreading Modulation for Multilevel Nonvolatile Memories · IEEE Trans. Commun. 2016 |
Content delivery and video streaming › caching
coded caching |
0.1 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Content delivery and video streaming
peak traffic reduction |
0.1 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Coding theory › error-correcting codes
erasure coding |
0.1 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Coding theory › error-correcting codes › block codes
MDS codes |
0.1 | 1 | 2019 | Coded Caching With Distributed Storage · IEEE Trans. Inf. Theory 2019 |
Coding theory › sequences › sequence design › sequence family construction
orthogonal codes |
0.1 | 1 | 2016 | Spreading Modulation for Multilevel Nonvolatile Memories · IEEE Trans. Commun. 2016 |
Coding theory › sequences › sequence design
spreading sequences |
0.1 | 1 | 2016 | Spreading Modulation for Multilevel Nonvolatile Memories · IEEE Trans. Commun. 2016 |
Methods — techniques the papers use, named apart from their topics
MDS erasure codes · 0.8spreading modulation · 0.5inter-cell-interference mitigation · 0.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2019 | Coded Caching With Distributed StorageabstractContent delivery networks store information distributed across multiple servers, so as to balance the load and avoid unrecoverable losses in case of node or disk failures. Coded caching has been shown to be a useful technique which can reduce peak traffic rates by pre-fetching popular content at the end users and encoding transmissions so that different users can extract different information from the same packet. On one hand, distributed storage limits the capability of combining content from different servers into a single message, causing performance losses in coded caching schemes. But, on the other hand, the inherent redundancy existing in distributed storage systems can be used to improve the performance of those schemes through parallelism. This paper designs coded caching and delivery schemes tailored towards systems where the library is distributed across multiple servers, possibly with some redundancy in the form of maximum distance separable (MDS) erasure codes. Different schemes are proposed based on the capacity of the users’ caches, as well as the number of parity servers. The main focus is on scenarios with one (RAID-4) or two (RAID-6) parity servers, but the paper also includes simple extensions for cases with more than two or no parity servers at all. The proposed schemes are shown to reduce the worst case latency, or equivalently the peak transmission rate from any server, below that of state-of-the-art algorithms. Tianqiong Luo, Vaneet Aggarwal, Borja Peleato |
IEEE Trans. Inf. Theory | 1 |
| 2016 | Spreading Modulation for Multilevel Nonvolatile MemoriesabstractThe aggressive scaling of NAND flash memories has caused significant degradation in their reliability and endurance. One of the dominant factors in this degradation is the inter-cell-interference, by which the programming of a cell can affect nearby neighboring cells corrupting the information that they store. This paper proposes a new data representation scheme, which increases endurance and significantly reduces the probability of error caused by inter-cell-interference. The method is based on using an orthogonal code to spread each bit across multiple cells, resulting in lower variance for the voltages being programmed in the cells. This new data representation method is also shown to present many of the advantages that spreading sequences bring to wireless communications. For example, multiple information sequences can be written on the same cells at different times without interfering with each other. It also allows storing additional information on an already programmed memory in such a way that the new information is hidden by the noise. Tianqiong Luo, Borja Peleato |
IEEE Trans. Commun. | 1 |
| 2015 | Spread programming for NAND flashabstractThe aggressive scaling of NAND flash memories has caused significant degradation in their reliability and endurance. One of the dominant factors in this degradation is the inter-cell-interference (ICI), by which the programming of a cell can affect near-by neighboring cells corrupting the information that they store. This paper proposes a new data representation scheme which increases endurance and significantly reduces the probability of error caused by ICI. The method is based on using an orthogonal code to spread each bit across multiple cells, resulting in a more uniform distribution of voltages being programmed in the cells. Tianqiong Luo, Borja Peleato |
ICC | 1 |