This article presents a novel generalized approach to obtain rational (dyadic and integer) bi-orthogonal wavelet filter coefficients based on two conditions, namely maximally flatness and near-perfect reconstruction (PR) in half-band polynomial (HBP). An incremental-iterative approach is adopted to design the coefficients based on the proposed error equation in terms of the remainder polynomial (RP) of Lagrange HBP and the proposed HBP with maximum vanishing moments (VMs). In addition, VLSI architecture for the proposed wavelet filter banks (FBs) is designed and implemented on the Zedboard ZYNQ-7000 AP-SoC (Zynq FPGA from Xilinx) field-programmable gate array. It is found that the proposed rationalized wavelet FBs achieved significantly low digital hardware requirements with similar characteristics when compared to well-known rationalized existing bi-orthogonal wavelet FBs. The effectiveness of the designed wavelet FBs is verified in image compression and image retrieval on well-known publicly available databases. It is found that the designed rationalized bi-orthogonal wavelet FBs give better performances when compared to existing rationalized bi-orthogonal wavelet FBs.

Gabor wavelet is widely used in the analysis of texture features. It is found that Gabor wavelet filter bank (FB) requires infinite precision (due to irrational coefficients) to extract accurate directional textural features for which it needs numerous computations and external memory access. Due to this, there is a requirement for huge digital hardware, increased dynamic power dissipation, and increased processing time. In order to solve these issues, this article presents the first dyadic Gabor wavelet FB (DGWFB) based on the slight alteration in orientation parameter without disturbing the remaining Gabor wavelet parameters. In addition, this article introduces a separable VLSI architecture for the proposed DGWFB. The proposed VLSI architecture is implemented in field-programmable gate array (FPGA) through Xilinx Kintex 7 platform. It is observed that the proposed DGWFB has reduced processing time, dynamic power dissipation and digital hardware requirement significantly. The effectiveness of the designed DGWFB is evaluated in medical image retrieval application using three different publicly available medical databases namely NEMA, OASIS, and EXACT09. The proposed DGWFB achieved better performance as compared to existing Gabor wavelet FBs with significantly reduced digital hardware and processing time.

This paper presents a novel approach to obtain rational bi-orthogonal wavelet filter coefficients based on Perfect Reconstruction (PR) in Half-Band Polynomial (HBP) by removing Vanishing Moments (VM). A delta-error approach is adopted to design wavelet filter coefficients that reduce the error using an iterative method. This error equation is formulated in terms of generalized HBP, where the odd values are equated to zero and the filter coefficients are constrained with complete dyadic conditions. This produces a generalized design for bi-orthogonal filter with perfect reconstruction. Furthermore, in order to realize power-efficient designs, we propose a reversible logic based implementation for the proposed bi-orthogonal wavelet filter bank. The implementation efficiency is measured in terms of Gate Count (GC), Quantum Cost (QC), Ancilla Input (AI) and Garbage Output (GO). The proposed Design 2 is able to reduce (GC, QC, AI, GO) by (34.3%, 31.6%, 33.9%, 31.1%) when compared to existing design. The effectiveness of the proposed wavelet Filter Banks (FBs) is verified using an image compression application. The experimental results show that, the proposed rationalised wavelet FBs are able to achieve an average increase of 16% in PSNR when compared to existing designs.

This paper presents a generalized novel design of a family of multiplier free orthogonal wavelet filter banks (FBs) with low complexity. In the proposed method, maximum number of zeros at$z=-1$is ensured for a desired length of analysis and synthesis filters. A new class of technique is proposed to obtain dyadic filter coefficients based on double shifting orthogonality property with allowable deviation from original filter coefficients. This is achieved by slightly altering perfect reconstruction (PR) condition to obtain dyadic filter coefficient. A general closed form expression is formulated using double shifting orthogonality property to reduce the error between original filter coefficients and proposed dyadic filter coefficients. The designed wavelet FB improved time-frequency product, Sobolev regularity and frequency selectivity (low energy in error) over well known existing wavelet FBs. In addition, a fixed point VLSI architecture is proposed for the designed family of orthogonal wavelet FBs. The suggested architecture is designed and implemented on Kintex7 FPGA board. The proposed family of orthogonal wavelet FBs is multiplier less with significantly reduced adders, shifters and dynamic power dissipation. The performance of the proposed wavelet FB is validated on two different applications namely image compression and medical image retrieval. The proposed FBs are tested on well known datasets such as CLASSIC, EPFL, RAISE, and FiveK for image compression and on three different medical image databases such as NEMA, OASIS, and EXACT09 for image retrieval.

This study presents the implementation of image kernels used for filtering and enhancing the images using reversible logic gates, a first in reversible logic literature. Image enhancement/filtering is achieved by performing convolution of an image with a filter kernel. This work proposes reversible logic based design and implementation of six filter kernels. The filter kernels implemented are Gaussian blur, Laplacian outline, Sobel, Emboss, Sharpen and Prewitt edge detection. The kernels are implemented individually using reversible logic gates and the designs are measured in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The functional verification is carried out using standard images on Kintex 7 FPGA platform. The filtered images from the proposed design have an average structural similarity index of 0.92.

The design of wavelet filter‐bank in real continuum domain demands infinite precision to achieve perfect reconstruction (PR). The computations with irrational coefficients in orthogonal filters require a large amount of hardware that result in increased power dissipation, huge memory requirements and reduction in speed of operation. This paper presents a new approach to obtain a complete dyadic (low complexity) 6‐tap orthogonal symmetric wavelet filter‐bank (FB) with near perfect reconstruction. This is achieved by slightly altering the PR conditions to make orthogonal filters symmetric and to obtain complete dyadic filter coefficients. The proposed wavelet FB has reduced dynamic power dissipation and significantly reduced adder and shifter count. The VLSI architecture of the proposed FB is designed and implemented on Kintex‐7 FPGA. The architectural design is carried out using Verilog and functional simulation and synthesis are executed using Vivado 2016.4 software. The proposed FB dissipates 114mW dynamic power and requires only 5 adders and 3 shifters. The effectiveness of the proposed wavelet is verified in three different applications namely image compression, iris recognition system and orthogonal frequency division multiplexing (OFDM). The proposed wavelet FB gives comparable performance in image compression and attains superior performance in iris recognition system (feature extraction) and OFDM.

Color space conversion is an age old technique used to achieve ease in processing, feature extraction, compression and storage of image and video data. One such color space conversion is RGB to gray scale conversion. Gray scale representation of images aids in reducing storage space and increasing speed of operation. This paper presents a color space conversion scheme using reversible logic gates. An RGB color space to gray scale color space conversion using color channel averaging method and color space desaturation method is implemented in this paper. Reversible logic/computations have emerged as a major alternative to decrease the power dissipation in digital circuits. Reversible sub modules like 8-bit adder, comparator, shifter etc are used to implement the color space conversion. The implementation of reversible logic circuits was done and the functionality verification was done on Kintex 7 FPGA platform. The results are projected in terms of gate count, ancilla input, garbage output and quantum cost for reversible implementation and in terms of hardware utilization and power for FPGA. The proposed reversible circuit complies with the color conversion standards and can find application in any low power image and video processing applications.