Triple Modular Redundancy (TMR) is a common approach to mitigate the effects of Single-Event Upsets (SEUs) in SRAM-based Field-Programmable Gate Arrays (FPGAs), where these faults may cause changes in the configuration of logic or interconnect resources. Partial TMR aims at balancing SEU mitigation with redundancy costs. This work introduces a Design-Space Exploration (DSE) approach that automatically generates and evaluates cost-reliability-optimized, Pareto-optimal partial TMR configurations of modules in a hierarchical design. The approach is evaluated using a proof-of-concept implementation for AMD’s 7 Series FPGAs and five case-study designs, including the NEORV32 RISC-V CPU. Multiple fitness assignment variants – based on static bitstream analysis, (statistical) fault injection results, and a combined approach –-are compared regarding effectiveness and runtime. Comparing the hypervolumes of the generated Pareto fronts of the final generation and a randomly generated starting generation, the approach improves cost-effectiveness of the generated TMR solutions by 17%–52%, delivering an attractive benefit-cost-ratio. The presented approach effectively generates a diverse set of TMR solutions across a wide cost-reliability range, allowing the designer to choose a variant that best fulfills the application’s, mission’s, or mission phase’s cost-reliability requirements.

Drones are powerful tools for a plethora of applications ranging from photography to agriculture and disaster response. Ever-advancing progress in the fields of highly integrated circuits and Artificial Intelligence (AI) acts as a multiplier for the autonomous operation of drones and the expansion of their application. In the context of undergraduate- and graduate-level teaching of electronic and mechatronic engineering, drones provide a remarkably compact and engaging example relating its many different (sub)disciplines. However, integrating drones into courses may pose challenges such as risk of injury or equipment damage, high unit and laboratory equipment costs, and the steep learning curve of implementing a flying machine “from scratch”. Nevertheless, interaction with real-world devices is essential for student engagement and learning experience. This work proposes a set of lab concepts comprising technical and teaching solutions that aim at facilitating the integration of drones into these fields of teaching. Applying these solutions allows students to effectively keep pace with the rapidly advancing Uncrewed Aerial Vehicle (UAV)-related developments in their respective fields of study.

While the vulnerability of SRAM-based FPGAs against soft errors affecting their configuration is a well-known issue, robustness analysis techniques and fault mitigation approaches for these devices predominantly focus on Xilinx/ AMD devices, making use of vendor-supplied analysis tools and fault injection infrastructure. This work presents a robustness analysis approach centered on entirely open-source FPGA synthesis, implementation, analysis, and configuration tools, as well as open-source device documentation. It demonstrates this approach - based on bitstream-level fault modeling and empirical intercon-nect fault characterization - on Lattice Semiconductor's low-power, low-cost, mid-size ECP5 FPGA technology. The proposed approach is evaluated on a NEORV32 RISC-V CPU design, showing that the predictions made by the approach reduce fault injection workload by up to 90%. Furthermore, the approach facilitates detailed fault analysis, both on the configuration level (by configuration bit - or fault - category) and on the structural level (by affected netlist module). To the best of our knowledge, the presented approach is the first comprehensive soft-error robustness analysis approach for a modern non-AMD SRAM-based FPGA technology,

A significant portion of the configuration memory of modern SRAM-based FPGAs is dedicated to configuring the interconnect. Understanding the effects of interconnect-related Single-Event Upsets (SEUs) on the circuit's behavior is critical for developing accurate reliability prediction and efficient fault mitigation approaches. This work describes an approach to classify the effects of single-bit interconnect faults into well-known fault models, and to characterize the electrical effects of these modeled faults. An experimental fault characterization for two families of Xilinx and Lattice FPGAs shows that different types of single-bit interconnect faults exhibit significantly different criticality. This may serve as a partial explanation for the large discrepancies reported in literature between faults predicted to be critical by state-of-the-art methods (“essential bits”) compared to the numbers of actually critical bits determined experimentally and may be used to improve prediction accuracy or reliability-aware routing approaches.

The configurable interconnect of SRAM-based FPGAs makes up a significant portion of their configuration, and thus exposes a large attack surface to single-event upsets. A better understanding of the behavior of FPGA interconnects under the presence of these faults may allow fault injection campaigns and reliability estimation techniques to treat some interconnect faults as more serious than others. This work proposes an approach to (1) analyze the interconnect configuration of a given FPGA technology to deduce the logical effects caused by single-bit flips and (2) to characterize the effects of such faults on routes implemented on a given FPGA technology. These approaches are illustrated in case studies on two FPGA technologies: Xilinx 7 Series and Lattice iCE40. Characterization of interconnect faults on these devices revealed that certain subcategories of interconnect fault types are far more critical than others, allowing more focused fault injection campaigns. Applying this knowledge to three benchmark designs implemented on a Xilinx 7 Series device shows that fault injection effort can be significantly reduced by skipping bits that are unlikely to critically impact the design.

Systematic fault injection into the configuration memory of SRAM-based FPGAs promises to gain insight into the criticality of individual configuration bits. Current approaches implicitly assume that results obtained on one FPGA device can be generalized to all devices of that type and hence allow to parallelize fault injection. This work, to the best of our knowledge, is the first to challenge this assumption. To that end, a synthetic test design was subjected to systematic fault injection on 16 Xilinx Artix-7 as well as 10 Lattice iCE40 FPGAs for which bitstream documentation is publicly available. The results of these experiments indicate that the derived sets of critical configuration bits vary from device to device of the same type, especially if the interconnect is targeted. Furthermore, temperature is observed to influence the fault injection results on Artix-7. Suggestions for dealing with the implications in future fault injection experiments are provided.

Basic Linear Algebra Subprograms (BLAS) has emerged as a de-facto standard interface for libraries providing linear algebra functionality.The advent of powerful devices for Internet of Things (IoT) nodes enables the reuse of existing BLAS implementations in these systems.This calls for a discerning evaluation of the properties of these libraries on embedded processors.This work benchmarks and discusses the performance and memory consumption of a wide range of unmodified open-source BLAS libraries.In comparison to related (but partly outdated) publications this evaluation covers the largest set of opensource BLAS libraries, considers memory consumption as well and distinctively focuses on Linux-capable embedded platforms (an ARM-based SoC that contains an SIMD accelerator and one of the first commercial embedded systems based on the emerging RISC-V architecture).Results show that especially for matrix operations and larger problem sizes, optimized BLAS implementations allow for significant performance gains when compared to pure C implementations.Furthermore, the ARM platform outperforms the RISC-V incarnation in our selection of tests.