To reduce defect parts per million (DPPM) on IC products, IDDQ testing can be exploited for identifying the outliers which are potentially defective but not detected by sign-off functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical$6\sigma $rule or engineers’ experience are usually too conservative to effectively identify nontrivial outliers, especially, when spatial correlations are of great concern/influence. In article, an improved convolutional neural network (CNN)-based method can be proposed for IDDQ outlier identification. In the proposed method, the mean and the standard deviation on the IDDQ value inside a die under test (DUT) can be predicted by employing a stochastic regression model. According to the predicted mean and standard deviation, we derive an expected IDDQ interval and identify the DUT as an outlier if its actual measured IDDQ value is beyond the expected interval. From the observation of the experimental results, the improved data preprocessing and the improved CNN-based stochastic regression can be contained to enhance the prediction accuracy of the expected IDDQ intervals. In the improved method, the spatial correlations of the neighboring dice inside a window can be considered by training a CNN-based stochastic regression model with a large volume of industrial data on 28 and 65 nm products. The trained model is highly accurate prediction in the$R^{2}$(0.973) and RMSE (0.626 mA) of the expected IDDQ values on 28 nm product and the$R^{2}$(0.942) and RMSE (2.155 uA) of the expected IDDQ values on 65 nm product. Furthermore, the experimental results show that the trained model can capture the potential defective dice by identifying efficient IDDQ outliers.

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.

GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate neighbors or exploiting simple linear regression, in this paper we propose to employ a window of larger size for broad-sighted recognition of neighborhood, and make best use of the larger window for accurate prediction of the suspicious level for any given die. The proposed methodology is realized by using an artificial neural network (NN), and is a breakthrough of NN-based work for solving the problem of GDBN. Various experiments on two sets of data clearly reveal the superiority of our NN-based methodology over other existing methods. Besides reducing DPPM, our methodology is able to achieve 1. 5X-2X better reduction in the cost for return merchandise authorization (RMA).

In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.

In this paper, we present a mixed-height standard cell placement flow for digital circuit blocks. To our best knowledge, commercial tools currently do not support this type of flow in a fully automated manner. In our placement flow, we leverage a commercial placement tool and integrate it with several new point tools. Promising experimental results are reported to demonstrate the efficacy of our placement flow.

In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.

Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building blocks and model the behavior of each block easily. Although the regression efforts have been greatly alleviated in this structure-based approach, the preparation of the training patterns is still a big issue. In this work, a different approach is proposed to build the behavioral model of each internal block in structure-based approach without regression. Therefore, no training patterns are required in the calibration process. As shown in the experimental results, the model accuracy is still kept in the proposed approach while the efficiency of behavioral model generator is greatly improved.