Summary Approximate computing enhances the performance and energy efficiency of applications, while still achieving acceptable accuracy. Some of the multithreaded applications can tolerate the accuracy loss when critical sections are approximately executed, which in turn will eliminate the synchronization overhead of these applications and increase their performance. In this study, our objective is to explore the behavior of the critical sections and selectively skip the ones yielding performance improvements with an acceptable accuracy loss. We have observed the behavior of 62 critical sections of 4 selected applications. We have grouped them depending on their effects on program execution and skipped or approximated them accordingly. Our experimental study indicates that skipping 76% of the critical sections offers 2.5 performance gain with 16% accuracy loss for Raytrace whereas 1.4 performance improvement with 17% accuracy loss is obtained for Radiosity on average when 36% of the critical sections are skipped. For Water_NSquared the performance gain is 1.1 with 9% accuracy loss on average with 79% of critical sections skipped. For the Ocean_CP application we see a performance improvement of 1.6 with accuracy loss 1% when we skip 38% of critical sections.

Summary Redundant multithreading (RMT) is an effective thread‐level replication method to improve the reliability requirements of applications. Although it significantly improves the robustness of applications, it comes with additional performance overhead since the redundant threads might share the same core resources. In our previous study [Efficient selective replication of critical code regions for SDC mitigation leveraging redundant multithreading.J Supercomput2021;77:14130‐14160], we presented an efficient software‐level RMT approach, where we execute the most critical code regions with three threads to correct errors. In this study, we focus on further improving the performance of our software‐level RMT method by presenting a set of different thread‐to‐core mapping alternatives. We provide different static mapping methods, which require preliminary information about the applications, such as execution time, instruction‐per‐cycle (IPC), or cache usage patterns, and a set of dynamic mapping methods, which map threads to cores dynamically at runtime without requiring any additional information. The dynamic mapping methods decide which threads are mapped to which cores at each scheduling point based on the IPC, cache miss rate, or cache access values of each thread as well as each core. Experimental results show that the dynamic mapping method, which maps threads to cores based on IPC values, outperforms all other static and dynamic methods. It also outperforms our baseline model, where the operating system handles the thread‐to‐core mappings by 8%, 7%, and 20% based on average speedup, harmonic speedup, and mean slowdown metrics.

The small feature sizes in current Networks-on-chip (NoCs) have increased the importance of reliability. However, existing fault tolerance schemes incur costs in terms of performance and power consumption which can be over-burdening. In order to tackle the reliability problem in NoCs while minimizing the performance and energy costs, a compiler-enhanced reliability scheme is introduced in this paper which assigns extra protection only to data transmissions in NoC which are considered critical. The experimental study validates that our scheme yields almost equal level of fault tolerance for critical data transmissions with the scheme that protects all packet transmissions indiscriminately. Our scheme is also shown to have better performance by approximately 7% than the conservative scheme for the tested criticality annotation.