Modern real-time embedded systems increasingly use runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, reconfiguration delay is non-negligible and varies due to resource contention. Unlike existing solutions that affect system resources or timing, this paper presents an approach and tools to provide a safe, tight reconfiguration delay bound by accurately modeling contention, without additional resource usage, and applicable to most embedded Systems-on-Chip. Additionally, by using Quality-of-Service mechanisms available in modern systems-on-chip, the proposed approach allows designers to set an upper limit for the reconfiguration delay and maintain it against interference from competing tasks. To evaluate the proposed approach, we present two experiments in which it is applied to a representative configuration on a Xilinx Zynq UltraScale+ platform. Experimental results indicate that the reconfiguration delay bound holds under induced worst-case interference scenarios, ensuring that, under heavy workload conditions, the reconfiguration delay can be up to 6.3 times its value in isolation. Moreover, the approach can automatically generate a quality-of-service configuration that ensures a maximum reconfiguration delay 1.8 times its value in isolation, with only a 14% slowdown on contenders and no additional resource consumption, outperforming the existing state of the art. • An approach to emulate worst-case contention for Dynamic-Partial Reconfiguration. • A tool to inject traffic and characterize Dynamic Partial Reconfiguration delay. • QoS-based mitigation ensuring timing isolation for Dynamic Partial Reconfiguration.

As embedded systems are required to satisfy increasing functional and non-functional requirements, heterogeneous systems-on-chip architectures are progressively adopted. While these complex systems-on-chip deliver high performance, they require efficient coordination of the tasks they carry out. To tackle this challenge, designers often resort to runtime mechanisms allowing the dynamic alignment of application requirements with platform services. In turn, runtime mechanisms require the adoption of on-chip monitoring systems. The integration of on-chip monitoring systems into a system-on-chip results in a monitored system-on-chip. Notwithstanding, this integration risks driving a re-design and a re-implementation of the whole system-on-chip, potentially driving to a time-to-market deadline miss. In the literature, HW/SW co-design approaches for monitored systems-on-chip have been proposed to overcome the problem. However, the existing HW/SW co-design approaches prevent performing a system-level design-space exploration that involves all the monitoring requirements, and they also prevent adequate reuse of existing on-chip monitoring systems. This article proposes an approach for efficient HW/SW co-design of monitored systems-on-chip, aiming to comprehensively capture all monitoring requirements at the system-level and to perform a system-level design-space exploration to satisfy them, enforcing the reuse of existing on-chip monitoring systems. The proposed approach is validated through two experimental activities, which demonstrate a 24% reduction in total development time for a monitored system-on-chip implemented on FPGA, compared to the customary approach. The results also show that the approach reduces the risk of missing time-to-market deadlines, supports flexible design choices, and enables the reuse of on-chip monitoring systems.

Commercial embedded systems increasingly rely on heterogeneous architectures that integrate general-purpose, multi-core processors, and various hardware accelerators on the same chip. This provides the high performance required by modern applications at a low cost and low power consumption, but at the same time poses new challenges. Hardware resource sharing at various levels, and in particular at the main memory controller level, results in slower execution time for the application tasks, ultimately making the system unpredictable from the point of view of timing. To enable the adoption of heterogeneous systems-on-chip (System on Chips (SoCs)) in the domain of timing-critical applications several hardware and software approaches have been proposed, bandwidth regulation based on monitoring and throttling being one of the most widely adopted. Existing solutions, however, are either too coarse-grained, limiting the control over computing engines activities, or strongly platform-dependent, addressing the problem only for specific SoCs. This article proposes an innovative approach that can accurately control main memory bandwidth usage in FPGA-based heterogeneous SoCs. In particular, it controls system bandwidth by connecting a runtime bandwidth regulation component to FPGA-based accelerators. Our solution offers dynamically configurable, fine-grained bandwidth regulation – to adapt to the varying requirements of the application over time – at a very low overhead. Furthermore, it is entirely platform-independent, capable of integration with any FPGA-based accelerator. Developed at the register-transfer level using a reference SoC platform, it is designed for easy compatibility with any FPGA-based SoC. Experimental results conducted on the Xilinx Zynq UltraScale+ platform demonstrate that our approach (i) is more than$100\times$faster than loosely-coupled, software controlled regulators; (ii) is capable of exploiting the system bandwidth 28.7% more efficiently than tightly-coupled hardware regulators (e.g., ARM CoreLink QoS-400, where available); (iii) enables task co-scheduling solutions not feasible with state-of-the-art bandwidth regulation methods.

Electronic Design Automation (EDA) is a crucial research area related to the development of electronic systems. In particular, High-Level Synthesis (HLS) simplifies HW design by automatically translating C/C++/System C specifications into HW description languages. However, HLS for large systems can be time-consuming. In recent years, Machine Learning (ML) has emerged as a prominent topic in EDA, with numerous studies demonstrating its potential to enhance EDA methods covering nearly all phases of the HW design flow. In such a context, this work presents an approach and related frameworks to collect datasets (i.e., SLIDE-x) useful for performing HLS timing and resource estimation through ML techniques (i.e., SLIDE-x-ML), introducing a data-driven component for feature creation that enhances predictions through various input representations and ML methods.

Embedded systems are increasingly adopting heterogeneous templates integrating hardware accelerators and application-specific processors, which poses novel challenges. In particular, it is difficult to have accurate control of task activities in Commercial Off-the-shelf (COTS) System on Chips (SoCs), due to complex main memory sharing mechanisms among different computing engines. To address this problem, bandwidth regulation approaches based on monitoring and throttling are widely adopted. Existing solutions, however, are either too coarse-grained, limiting the control over computing engines activities, or platform-dependent, addressing the problem only for specific SoCs. In this paper we propose an innovative, fine-grained and platform-independent approach that can accurately control main memory bandwidth usage in an FPGA-based Heterogeneous System on Chip (HeSoC). Experimental results conducted on the Xilinx Zynq UltraScale+ platform demonstrate that our approach enables solutions not feasible with state-of-the-art bandwidth regulation methods.

The objective of the FRACTAL project is to create a novel approach to reliable edge computing. The FRACTAL computing node will be the building block of scalable Internet of Things (from Low Computing to High Computing Edge Nodes). The node will also have the capability of learning how to improve its performance against the uncertainty of the environment. In such a context, this paper presents in detail one of the key use cases: an Internet-of-Things solution, represented by intelligent totems for advertisement and wayfinding services, within advanced ICT-based shopping malls conceived as a sentient space. The paper outlines the reference scenario and provides an overview of the architecture and the functionality of the demonstrator, as well as a roadmap for its development and evaluation.

Nowadays, complex Cyber-Physical Systems (CPSs) often exploit the so-called computing at the edge (i.e., edge-computing), where the Dynamic Partial Reconfiguration (DPR, also known as Dynamic Function eXchange or Partial Reconfiguration) feature has been proved to be efficient to face the adaptivity challenges typical of the CPSs domain. In this context, the increase of both platforms heterogeneity and required customizations are leading to a growth of the number of per-task requested DPR, for which Industry is enhancing the reconfiguration controllers providing the capability to offload more than one DPR request, in turn allowing pipelining between multiple DPR processes and application execution. Several works in literature have introduced the DPR process in the hard real-time system domain, however not considering the multiple DPR offloading capabilities. In this paper, we provide a theoretical analysis and a practical evaluation of multiple DPR offloading in the context of hard real-time systems. In particular, through a motivational case-study, supported by some experimental activities conducted on the Zynq-7000 SoC, we show how the offload of multiple DPR can provide benefits with respect to the traditional approach of one DPR request per time.

Advanced computations on embedded devices are nowadays a must in any application field. Often, to cope with such a need, embedded systems designers leverage on complex heterogeneous reconfigurable platforms that offer high performance, thanks to the possibility of specializing/customizing some computing elements on board, and are usually flexible enough to be optimized at runtime. In this context, monitoring the system has gained increasing interest. Ideally, monitoring systems should be non-intrusive, serve several purposes, and provide aggregated information about the behavior of the different system components. However, current literature is not close to such ideality: For example, existing monitoring systems lack in being applicable to modern heterogeneous platforms. This work presents a hardware monitoring system that is intended to be minimally invasive on system performance and resources, composable, and capable of providing to the user homogeneous observability and transparent access to the different components of a heterogeneous computing platform, so system metrics can be easily computed from the aggregation of the collected information. Building on a previous work, this article is primarily focused on the extension of an existing hardware monitoring system to cover also specialized coprocessing units, and the assessment is done on a Xilinx FPGA-based System on Programmable Chip. Different explorations are presented to explain the level of customizability of the proposed hardware monitoring system, the tradeoffs available to the user, and the benefits with respect to standard de facto monitoring support made available by the targeted FPGA vendor.

The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.

Cyber-Physical Systems (CPS) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, smart, adaptive, predictive and react in real-time. Indeed, as sight for human beings, image- and video-processing pipelines are a prime source for environmental information for systems allowing them to take better decisions according to what they see. Therefore, in FitOptiVis we are developing novel methods and tools to integrate complex image and video processing pipelines. FitOptiVis aims to deliver a reference architecture for describing and optimizing quality and resource management for imaging and video pipelines in CPS both at design- and run-time. The architecture is concretized in low-power, high-performance, smart components, and in methods and tools for combined design-time and run-time multi-objective optimization and adaptation within system and environment constraints.

In the domain of Cyber-Physical Systems, the FPGA Dynamic Partial Reconfiguration (DPR) feature has been proved to be efficient to adapt the system hardware configuration to environment changes, also in the case of hard real-time constraints. Often, in this context, a single task can request multiple DPR to modify the platform configuration.However, also if in the hard real-time literature several works exploit the DPR process, to the best of our knowledge, no one deals with its scalability (i.e., the efficient management of multiple DPR requests).Hence, in this work, focusing on hard real-time systems, we conduct both a theoretical and practical investigation about the DPR scalability, discussing the obtained outcomes and the objectives to be achieved in the near future.

This work faces the role of Design Space Exploration for embedded systems based on heterogeneous parallel architectures and subject to mixed-criticality system requirements, while considering the exploitation of hypervisor-based SW partitions to better manage isolation. In particular, it presents an evolutionary partitioning and mapping approach integrated into a reference Electronic System Level HW/SW Co-Design framework to propose and early validate design solutions by means of HW/SW Co-Simulations.

Nowadays embedded systems are powerful and everywhere. They implement complex functionality relying on a huge set of different hardware and software (HW/SW) architectures. In order to reduce their development effort, HW/SW Co-Design techniques are used during the entire development cycle. These techniques aim at helping designers to define a feasible hardware and software partitioning for the system in such a way that functional and non-functional requirements are fulfilled. In this context Design Space Exploration is a challenging activity since a huge number of different implementation alternatives need to be evaluated.

Timing analysis of embedded systems is an operation performed when there are tasks that have to execute with a well precise deadline, and need to be scheduled, such as those on real-time systems. The diffusion of embedded systems to different kind of application areas is driving platforms toward heterogeneous multi-core architectures, that require a timing analysis done by using measurement based techniques. Measurements collection, when done via an instrumentation of the application, can cause an overhead in the execution time, footprint and necessary space to store data, that can affect the behaviour of the system. In such a scenario, this work proposes a framework that allows a user to quickly perform instrumentation choices, by using a concept named Time Band, and to have a direct feedback about the impact of its choices on some performance parameters. Time Band is then applied to Rapitime, a diffused timing analysis tool, and first tests have been done on IA-32 and PowerPC architectures, showing the advantages of different techniques the can be applied to realize the framework.

In recent years, embedded applications have been characterized by increasingly stringent requirements, both from functional and non-functional point of view. This led to the adoption of complex hardware platforms (multi-core and many-core architectures), able to guarantee high computational power with low energy consumption and reduced footprint. An efficient characterization of these platforms can be problematic, given the large number of hardware resources and the complexity of software applications. For this reason, the need for a runtime analysis support should be taken in account during the design phase (a design "for monitorability"). This paper introduces "Adaptive Profiling Hardware Sub-system" (AIPHS), a hardware profiling tool supporting the development of runtime monitorable systems. Two different multicore platforms are considered in order to evaluate AIPHS functionalities: an asymmetric dual-MicroBlaze system and a quad-Leon3 system supporting symmetric multiprocessing.

The presented Ph.D. work deals with the development of a framework to support the design of embedded systems. In particular, it focuses on the development of a unobtrusive profiling system to support, at run-time, both the definition of the best execution platform and its resource optimization. The final goal is the definition of a framework exploiting reconfigurable logic, based on monitoring actions and run-time decisions. The profiling system under development and its high portability toward different architectures, representing current status of Ph.D. work, are described. Planned future steps, including benchmarking by means of industrial applications, are illustrated.