Most existing visual object tracking (VOT) approaches are implemented based on the von Neumann computation systems, which inevitably have the problems of high latency. Additionally, remote server processing of video resources requires a large amount of data transmission over the Internet, which limits real-time tracking performance. The integration of VOT technology into electronic devices has become a new trend. However, current VOT approaches have high algorithm complexity, making it difficult to design the circuits to implement the corresponding functions. In this article, a memristor-based attention network (MAN) and its corresponding algorithm are proposed to achieve online real-time tracking under parallel computing. Memristors are used to construct the attention encoding circuits to record changes of the target in historical frames, and adjust attention signals to the target online and in real-time during the tracking process, avoiding the latency problem of the von Neumann architecture. Inspired by the working process of$\gamma $-GABAergic interneuron and tripartite synapse, we propose an attention allocation module to selectively allocate attention values. Combining the winner-take-all principle, we design a target localization circuit and an optimal attention zone selection circuit for the parallel computation to track the location of the target. Finally, the experiments and analyses on the OTB-100, NFS, and VOT-RTb2022 benchmark datasets verify that the proposed MAN has promising tracking performance and achieves a tracking speed of 1000 frames per second, demonstrating superior real-time performance.

The brain emotional learning network offers several advantages when compared to traditional neural networks. It features a simpler structure, low computational complexity, and fast training speed. These characteristics make it ideal for applications like pattern recognition, data classification, and intelligent control. However, current brain emotional learning networks, including their modified networks, are not capable of recognizing or classifying data in complex environments. To address this issue, this paper proposes a brain emotional learning network with an attention mechanism that strengthens the processing of key information while suppressing interfering information, thereby enabling the network to recognize data within complex environments. Furthermore, software implementation of neural networks often experiences slow computing speeds due to the separation of storage and computation in traditional von Neumann computers. To combat this issue, the paper presents a hardware circuit implementation of the attention mechanism-based brain emotional learning network using memristors. Finally, the designed in-memory computing neural network has been successfully applied to the recognition of traffic signs within complex environments, and has achieved accurate and rapid recognition.

Memristors, with their unique nonlinear characteristics, are highly suitable for construction novel neural models with rich dynamic behaviors. In this paper, a memristor with piecewise nonlinear state function is introduced into the tabu learning neuron model, resulting in a novel memristive tabu learning neuron model capable of generating a double-wing chaotic butterfly. By modulating the state function of the memristor, we can effectively and easily alter the number of wings of the chaotic butterfly. Equilibrium points analysis further elucidates the mechanism behind the generation of multi-wing chaos. Various numerical simulation techniques, including phase portraits, bifurcation diagrams, Lyapunov exponent spectra, and local attraction basins, are employed to illustrate the dynamical behaviors of the proposed model. Moreover, the newly constructed neuron model is validated using FPGA hardware, with the results aligning with numerical simulations, thereby offering a dependable foundation for a memristor digital circuit-based brain-like neuron model. Lastly, an image encryption application based on the multi-wing chaotic butterfly is developed to demonstrate the potential application of the model.

Natural Language Processing (NLP) plays a pivotal role in the realm of Digital Humanities (DH) and serves as the cornerstone for advancing the structural analysis of historical and cultural heritage texts. This is particularly true for the domains of named entity recognition (NER) and relation extraction (RE). In our commitment to expediting ancient history and culture, we present the “Chinese Historical Information Extraction Corpus”(CHisIEC). CHisIEC is a meticulously curated dataset designed to develop and evaluate NER and RE tasks, offering a resource to facilitate research in the field. Spanning a remarkable historical timeline encompassing data from 13 dynasties spanning over 1830 years, CHisIEC epitomizes the extensive temporal range and text heterogeneity inherent in Chinese historical documents. The dataset encompasses four distinct entity types and twelve relation types, resulting in a meticulously labeled dataset comprising 14,194 entities and 8,609 relations. To establish the robustness and versatility of our dataset, we have undertaken comprehensive experimentation involving models of various sizes and paradigms. Additionally, we have evaluated the capabilities of Large Language Models (LLMs) in the context of tasks related to ancient Chinese history. The dataset and code are available at https://github.com/tangxuemei1995/CHisIEC.

The high cost, low yield, and low stability of nanomaterials significantly hinder the application and development of memristors. To promote the application of memristors, researchers proposed a variety of memristor emulators to simulate memristor functions and apply them in various fields. However, these emulators lack nonvolatile characteristics, limiting their scope of application. This article proposes an innovative nonvolatile memristor circuit based on complementary metal–oxide–semiconductor (CMOS) technology, expanding the horizons of memristor emulators. The proposed memristor is fabricated in a reconfigurable array architecture using the standard CMOS process, allowing the connection between memristors to be altered by configuring theon–offstate of switches. Compared to nanomaterial memristors, the CMOS nonvolatile memristor circuit proposed in this article offers advantages of low manufacturing cost and easy mass production, which can promote the application of memristors. The application of the reconfigurable array is further studied by constructing an echo state network for short-term load forecasting in the power system.

Spiking neural networks (SNNs) are biologically plausible and computationally powerful. The current computing systems based on the von Neumann architecture are almost the hardware basis for the implementation of SNNs. However, performance bottlenecks in computing speed, cost, and energy consumption hinder the hardware development of SNNs. Therefore, efficient non von Neumann hardware computing systems for SNNs remain to be explored. In this article, a selective supervised algorithm for spiking neurons (SNs) inspired by the selective attention mechanism is proposed, and a memristive SN circuit as well as a memristive SNN circuit based on the proposed algorithm are designed. The memristor realizes the learning and memory of the synaptic weight. The proposed algorithm includes a top-down (TD) selective supervision method and a bottom-up (BU) selective supervision method. Compared with other supervised algorithms, the proposed algorithm has excellent performance on sequence learning. Moreover, TD and BU attention encoding circuits are designed to provide the hardware foundation for encoding external stimuli into TD and BU attention spikes, respectively. The proposed memristive SNN circuit can perform classification on the MNIST dataset and the Fashion-MNIST dataset with superior accuracy after learning a small number of labeled samples, which greatly reduces the cost of manual annotation and improves the supervised learning efficiency of the memristive SNN circuit.