Prototyping on FPGA has become a main stream verification methodology for hardware design, test development, software co-design etc. in the area of digital VLSI. In the case of test development, FPGA serves as a virtual DUT (Design under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE etc. Although, FPGA based platform is used widely for test program verification of digital ICs, this technique is not used for analog/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPFAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on FPGA. The proposed methodology exploits fixed-point modeling and DSP implementation technique facilitated by latest FPGAs to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of an analog phase locked loop (PLL) on Xilinx® Virtex"-4 FPGA. The FPGA emulation results show that performance of the emulated analog PLL (e.g., acquisition characteristics, step response) matches well with that of behavioral simulation.