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Qinjun Li

dblp:17/10449 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2025
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture		 0.912025
Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025
Processor architecture and microarchitecture
out-of-order execution		 0.912025
Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025
Processor architecture and microarchitecture › instruction set architecture › vector extension
RISC-V vector extension		 0.912025
Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025
Processor architecture and microarchitecture
vector processing		 0.312025
Titan-I: An Open-Source, High Performance RISC-V Vector Core · MICRO 2025
YearPublicationVenuePosition
2025 Titan-I: An Open-Source, High Performance RISC-V Vector Core
abstract
Vector processing has evolved from early systems like the CDC STAR-100 and Cray-1 to modern ISAs like ARM's Scalable Vector Extension (SVE) and RISC-V Vector (RVV) extensions.However, scaling vector processing for contemporary workloads presents challenges due to overheads in traditional architectures.We introduce Titan-I (T1), an out-of-order (OoO) RVV architecture designed
Jiuyang Liu, Qinjun Li, Yunqian Luo, Jiongjia Lu, Shupei Fan, Jianhao Ye, Yanqi Yang, Zewen Ye, Yuhang Zeng, Wei Cong, Xuecheng Zou, Mingyu Gao 0001
 MICRO2