The internet of underwater things (IoUT), a network of underwater objects, enables continuous and effortless monitoring of the oceans. The conventional IoUTs are battery-powered, which limits their lifetime and leads to environmental hazards when discarded. To address this, we propose a sustainable IoUT scheme that enables optical wireless charging of underwater nodes, extending the lifetime. The scheme utilizes optical wireless information and power transfer for data collection and charging IoUT nodes. An underwater optical wireless communication (UOWC) experiment is set up to demonstrate the optical wireless charging of an IoUT node and data acquisition from the node. The system’s performance under various underwater conditions is evaluated with blue, blue-green, and red lasers. The energy efficiency of the node is evaluated for different channel conditions by measuring the charging current using a battery charge monitor. The charging current varies with channel conditions, recording minimum values of 838.6mA at a maximum salinity of 35.2ppt, 838.3mA at a maximum Maalox concentration of 100mg/l, 839.5mA at a maximum channel temperature of 35°C, and 838.2mA at a maximum channel length of 2.5m.

Underwater wireless communication is an emerging domain of interest due to its exclusive applications in commercial ocean resource exploration, defence, oceanography, etc. Real-time communication systems demand high data rates, making underwater optical wireless communication (UOWC) a promising research domain. Typical UOWC links provide a very high data rate across a short range. This paper discusses the effect of underwater environmental conditions and the influence of different water types on the performance of underwater optical links. An underwater optical communication experimental setup is designed and implemented for real-time full-duplex video communication capable of dealing with real-time video call services. The system’s performance under various water conditions is evaluated with blue, blue-green, and red lasers. The mean square error (MSE), peak signal-to-noise ratio (PSNR), and structural similarity index (SSIM) for the received video stream at various channel conditions are evaluated using a video quality assessment tool.

Analog in-memory computing architectures demand high-speed analog-to-digital converters, for which a dynamic comparator is a crucial building block. Speed and common-mode insensitivity are the critical features of such dynamic comparators. Most of the reported dynamic comparators achieve high speed only for a narrow range of the input common-mode voltages. The comparators' performance degrades at the extremities of common-mode voltages. We propose a common-mode insensitive cascode cross-coupled dynamic comparator to overcome this drawback. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in a 65 nm CMOS technology. At 1.1 V supply voltage, the proposed comparator shows a delay of 37 ps when the input difference is 10mV with a common-mode voltage of 400mV.

Dynamic comparators are the core of high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. Most of the dynamic comparators attain high-speed operation only for sufficiently high input difference voltages. The comparators’ performance degrades at small input difference voltages due to a limited preamplifier gain, which is undesirable for high-speed, high-resolution ADCs. To overcome this drawback, a cascode cross-coupled dynamic comparator is proposed. The comparator improves the differential gain of the preamplifier and reduces the common-mode voltage seen by the latch, which leads to a much faster regeneration at small input difference voltages. The proposed comparator is designed, simulated, and compared with the state-of-the-art techniques in a 65 nm CMOS technology. The results show that the proposed comparator achieves a delay of 46.5 ps at 1 mV input difference, and a supply of 1.1 V.

Analog design can be considered as a multidimensional optimization problem since it involves trade-offs between several circuit parameters. Various optimization techniques have been proposed to reduce the cycle time of analog design. We propose a hybrid particle swarm optimization algorithm with linearly decreasing inertia weight for the optimization of analog circuit design. The proposed method is validated in a differential amplifier circuit with a current mirror load. Promising simulation results demonstrate that the proposed method can significantly reduce the design time required for analog circuits.