Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of circuit design, we consider them incomplete with two important aspects often being insufficiently addressed: 1) non-Gaussian distributions and 2) highly correlated parameters. To address these points, we propose a fully multivariate and non-Gaussian approach based on an arbitrary model. A subset of the model parameters is treated as a multidimensional random variable, which is represented by a combination of generalized lambda distributions and Spearman rank correlation matrices-a very general approach with nearly arbitrary freedom in distribution shapes and parameter correlations. In our application scenarios, we show that such a model is able to fully and accurately capture variability in device compact models and standard cell performance models. Finally, we present adapted analysis methods making use of these models in circuit simulations and in efficient gate level analyses of digital circuits with high accuracy.

We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, which enables TCAD-based transistor-cell co-design and path finding during the early phase of a technology node.

A set of analytical models based on the Pearson distribution function applied to the modeling of ion implantations in the 3-D structure of FinFETs is presented. The method provides a succinct way to simulate the doping profiles in FinFETs at low computational cost. Compared to previous analytical methods based on Gaussian distributions, this approach handles more realistic asymmetrical doping distributions arising from ion implantation. A simulation module in C++ has been developed to model ion implantations in FinFETs based on this analytical approach. The simulation module is demonstrated in an example simulation of a silicon-on-insulator FinFET with physical gate length of 20 nm.

Due to increased leakage currents and variability, classical bulk technology is reaching its scaling limits and some alternatives must be found. FinFETs are one of those alternatives. Through their 3D structure, they achieve better channel control which is the key to scalability. However, some sources of variability still remain. The impact of this technology shift on SRAM and DRAM memories is analyzed in this work.

This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET at 25, 18 and 13nm nodes are calibrated by a 3D atomistic device simulator with chip measurements of 35nm gate length devices. Synthesis results confirm that the variability of circuit performance will increase as device scaling continues, and can be more severe in new circuits at 18nm than in those stressed for a period of three years at 35nm. In addition, the results also reveal that increasing power consumption as adopted in adaptive supply voltage (ASV) and adaptive back bias (ABB) schemes is not a sustainable solution to compensate the drift in performance for future generations of CMOS circuits and systems.

Quantitative simulations of the statistical impact of negative-bias-temperature-instability (NBTI) on pMOSFETs, and positive-bias-temperature-instability (PBTI) on nMOSFETs are carried out for a 45nm low power technology generation. Based on the statistical simulation results, we investigate the impact of NBTI and PBTI on the degradation of the static noise margin (SNM) of SRAM cells. The results indicate that SNM degradation due only to NBTI follows a different evolution pattern compared with the impact of simultaneous NBTI and PBTI degradation.

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements.

We present for the first time an analytical model for the effect of short-gate transistor mismatch on analogue circuit design. Analogue circuit design is very vulnerable to device mismatch, as large numbers of matching-sensitive circuits are used. This is particularly severe in short-gate CMOS processes. In this paper, a new analytical mismatch model is developed for both triode and saturation regimes and verified using 35nm gate-length BSIM4 model cards. Short-channel effects, such as velocity saturation and mobility degradation, are taken into consideration. The results achieved excellent agreement with Monte Carlo HSPICE simulations. Furthermore, this model can be used to develop a rapid estimate of the precision or production yield of a circuit based only on the process statistics.

Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical parameter generation strategies in statistical circuit simulations. Results indicate that the typical use of uncorrelated normal distribution of the statistical compact model parameters may introduce considerable errors in the statistical circuit simulations.

Static statistical variability and time-dependent reliability are traditionally analyzed separately. This paper presents a new methodology which combines both types of variability within a single circuit analysis framework. A comprehensive Negative Bias Temperature Instability (NBTI) model was implemented. Effects of random discrete dopants, line edge roughness and poly-Silicon granularity were considered. Using a 74X-series benchmark circuit (4-bit fast-carry adder) as an example, the concept of integrating both static statistical variability and time-dependent reliability into circuit analysis is demonstrated.

In this paper we study the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of an inverter at the 45 nm technology generation using statistical circuit simulation. The impact of the variability on switching trajectories and propagation delay are studied using an inverter chain with differing Fan-Out/Fan-In (FO/FI) ratios.