A new breed of network intensive "e-science" applications are emerging that require a new perspective on how networks provide resources to the user. These e-science applications often have large raw capacity requirements (tens of gigabits/second) and require global reach. The discipline scientists expect this type of performance to be deterministic and repeatable, and available in conjunction with other resources such as sensors, instruments, computational clusters, storage arrays, and the like. The DRAGON project, an NSF funded testbed in the Washington DC metropolitan area, has been developing open source generalized multi-protocol label swapping (GMPLS) based service concepts that provide dedicated and deterministic network resources to the e-science application. Using the GMPLS control plane and DRAGON extensions, an entire "application specific topology" can be established in an automated fashion across administrative boundaries, across heterogeneous network technologies, and can be instantiated in seconds rather than weeks or months. This paper describes the technologies being developed by the DRAGON project and some of the ways application specific topologies are being applied to advanced networked applications.

We introduce a power-aware microsensor architecture supporting a wide operational power range (from10 W). The platform consists of a family of modules that follow a common set of design principles. Each module includes a local power microcontroller, power switches, and isolation switches to enable independent power-down control of modules and module subsystems. Processing resources are scaled appropriately on each module for their role in the collective system. Hard real-time functions are migrated to the sensor and radio modules for improved power efficiency. The optional Linux-based processor module supports high duty cycling and advanced sleep modes. Our reference hardware implementation is described in detail in this paper. Seven different modules have been developed. We utilize an acoustic vehicle tracking application to demonstrate how the architecture operates and report on results from field tests on tracked and wheeled vehicles.

One of the fundamental challenges for modern high-performance network interfaces is the processing capabilities required to process packets at high speeds. Simply transmitting or receiving data at gigabit speeds fully utilizes the CPU on a standard workstation. Any processing that must be done to the data, whether at the application layer or the network layer, decreases the achievable throughput. This paper presents an architecture for offloading a significant portion of the network, processing from the host CPU onto the network interface. A prototype, called the GRIP (Gigabit Rate IPSec) card, has been constructed based on an FPGA coupled with a commodity Gigabit Ethernet MAC. Experimental results based on the prototype are presented and analyzed. In addition, a second generation design is presented in the context of lessons learned from the prototype.