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Vera A. Zvereva

dblp:17/1675 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 40% Integrated circuit design · 20% Embedded and real-time systems · 20%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems › component-based systems
component communication
0.012004
Automatic Generation of Protocol Converters from Scenario-Based Specifications · RTSS 2004
Embedded and real-time systems
embedded system design
0.012004
Automatic Generation of Protocol Converters from Scenario-Based Specifications · RTSS 2004
Electronic design automation
high-level synthesis
0.012004
Automatic Generation of Protocol Converters from Scenario-Based Specifications · RTSS 2004
Electronic design automation › system-level design
IP reuse
0.012004
Automatic Generation of Protocol Converters from Scenario-Based Specifications · RTSS 2004
Integrated circuit design › system-on-chip
system-on-chip design
0.012004
Automatic Generation of Protocol Converters from Scenario-Based Specifications · RTSS 2004

Methods — techniques the papers use, named apart from their topics

systemc · 0.0message sequence charts · 0.0
YearPublicationVenuePosition
2004 Automatic Generation of Protocol Converters from Scenario-Based Specifications
abstract
Reuse of IP blocks is an important design philosophy for embedded systems. This allows shorter design cycles under tight time-to-market constraints. However, reusing IP blocks often requires designing converters (glue logic) to enable their communication. In this paper, we study the problem of automatically generating a protocol converter which enables various embedded system components (possibly with incompatible protocols) to talk to each other. Our work takes as input, a rich description of inter-component interactions described as a collection of message sequence charts. We then automatically synthesize from this input a protocol converter in SystemC. Our work is not restricted to uni-directional communication and the converter can be used to broker communication among many components. We demonstrate the feasibility of our approach by modelling some simplified bus protocols that capture key features of existing system-on-chip bus protocols. We then generate the bus controller as the protocol converter.
Abhik Roychoudhury, P. S. Thiagarajan, Vera A. Zvereva
RTSS4